The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper describes the modeling and design considerations of a low-power divide-by-two injection-locked frequency divider (ILFD) for 60GHz frequency synthesizer applications implemented in 90nm CMOS process. The paper proposes a divider's locking range model based on mixing analysis. The design uses a capacitor bank for the divider band selection and tail current injection. Measured results of the...
This paper presents the design and performances of two high speed high frequency dividers in a standard 60 nm RF technology. The dividers are part of a wireless receiver using a synthesizer with a reference frequency of 26 MHz and a voltage controlled oscillator with an output frequency of 6 GHz. The input operating frequency range of the dividers is 2-8 GHz. The minimum input voltage range is 250mV...
This paper presents a low power glitch-free dual-modulus (15/16) prescaler based on the phase-switching for Ultra-Wide Band (UWB) transceiver. An inherently glitch-free phase-switching prescaler is realized by the adoption of a reverse switching sequence without any additional complicated circuit. A simplified model of the source coupled logic (SCL) structure is proposed to optimize the power of the...
In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-2/3 prescaler is investigated. Based on this analysis, a new ultra low power wide band 2/3 prescaler is proposed and implemented using a GlobalFoundries 0.18 μm CMOS technology. Compared with the existing E-TSPC architectures, the proposed 2/3...
This paper presents a low power programmable frequency divider for use in implantable electronics operating in the 402 MHz to 405 MHz Medical Implant Communication Service (MICS) frequency band. The programmable divider was designed in IBM CMRF8SF 130 nm CMOS technology and simulated using Cadence Spectre circuit simulator. Subthreshold-source coupled logic has been used in this circuit for the first...
There is a need to use a truly adaptive analog-to-digital converter (ADC) to respond to any signal change and reduce the power consumption with less implementation complexity. The paper presents a front-end ASIC implementation for an adaptive control unit (ACU) for a reconfigurable ADC. The control unit is based on an adaptive algorithm that changes either the converter resolution or sampling-rate...
A low-power divide-by-4/5 unit of a prescaler is proposed. The power consumption and operating frequency of the extended true-single-phase-clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are analyzed. Compared with the existing design, a 20% reduction of power consumption is achieved. A divide-by-16/17 dual-modulus...
This paper presents a novel 2/3 divider cell circuit design for a truly modular programmable frequency divider with high-speed, low-power, and high input-sensitivity features. In this paper, the proposed flip-flop based 2/3 divider cell adopts dynamic E-TSPC circuit that not only reduces power consumption, but also improves operation speed and input sensitivity. The whole design was implemented using...
In this work a CMOS 1.2V 5GHz low-power voltage-controlled oscillator (VCO) is proposed. It uses an on-chip biased LC-tank topology and introduces a temperature compensation technique which stabilizes the oscillation amplitude for a robust I/Q generation using a frequency divider-by-2. Compared to a standard design with constant bias, it reduces the oscillation variation by almost two orders of magnitude...
This paper presents a phase-locked loop (PLL) used as a frequency synthesizer for a radio-frequency (RF) transceiver for use in the 5.7 ISM band, which were designed in the UMC RF 0.18 mum CMOS process. The PLL produces a set of different 16 digitally programmable frequencies in the [5424; 5830 MHz] frequency range. The low-power operation is achieved with the use of dynamic logic in the feedback...
This paper presents the design of a 10 GHz divider using Extended True Single Phase Clock (E-TSPC) logic on a 0.18 ??m CMOS technology with 1.8 V supply voltage. This divider contains D-Flip flop with dynamic structure that is based on the ??2 divider and ??8/9 dual modulus prescaler. By optimizing the transistor size in each divider stage and inserting optimized buffers between the stages, the power...
In this paper, a novel 4-modulus programmable frequency divider, suitable for millimeter wave PLL frequency synthesizer applications, is presented. The proposed frequency divider is designed using dynamic logic D flip-flop, and the divider is implemented in a standard 90 nm CMOS technology to achieve high frequencies of operation with very low power consumption. Measurements show a maximum input frequency...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
This paper presents the integration design and implementation of low-power voltage-controlled oscillator (VCO) and frequency divider for the Ku-band frequency synthesizer use. The integrated circuit is implemented by a 0.18 mum CMOS technology. To achieve the low-power consumption, the VCO core and the divider core are constructed in the complementary cross-coupled pair and in the injection-locked...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.