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A new reliable Electrostatic Discharge (ESD) power-rail clamp circuit has been proposed in this paper. The new circuit structure has achieved good results in reducing leakage current, anti-false triggering, increasing discharge transistor's turn on time. During the ESD event, the proposed circuit has a discharge time of 755.22ns, which is about 6.74 times that of conventional R-C power-rail clamp...
In this paper we propose and develop a complete solution to measure very low tunneling currents in Non-Volatile Memories, based on the Floating-Gate technique. We aim at using very basic tools (power supply, multimeter…) but still having a very good current resolution. The key node of our solution is that the experiment is led in a very particular low-noise environment (underground laboratory) allowing...
In this paper the analysis of DRAM logic compatible 3T cell has been shown. Due to its high density and low cost of memory, it is universally used by the advanced processor for on chip data and program memory. DRAM has transistor-capacitor cell structure, where capacitor is charged to produce 1 or 0. Memory array, which is arranged in row and column, is word line and bit line respectively. Here I...
Transistor scaling has enabled more memory to be embedded on-chip to accelerate large scale applications. However, increased leakage current in scaled technologies resulted in higher standby power consumption in volatile memories. Nonvolatile memories have been researched and developed as solutions to these problems. However, non-volatile memories such as Flash or magnetic spin torque memories require...
Novel DRAM cell with logic process compatible and whose memory operation is the same as the conventional DRAM operation is first time introduced. The cell uses the MOS capacitor with open base NPN bipolar transistor to amplify the storage capacitor. We fabricated the prototype cell and demonstrated the memory cell operation.
Power gating is an effective method to reduce leakage current in logic circuits during sleep mode. However, conventional power gating technique for minimizing leakage current introduces ground bounce noise during sleep to active mode transition. In this paper, a high performance stacking power gating structure is introduced which minimizes the leakage power and provides a way to control the ground...
SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy since there are no paths within the cell from Vdd to ground. Recently, DRAM cells have been...
This paper reviews recent experimental confirmations that the intrinsic radiation robustness of commercial CMOS technologies naturally improves with the down-scaling. When additionally using innovative design techniques, it becomes now possible to assure that performance and radiation-hardness are both met. An illustration is given with an original nano-power and radiation-hardened 8 Mb SRAM designed...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
BLT thin film capacitor was fabricated by the novel method of chemical mechanical polishing (CMP) process. The electrical characteristics including P-V and I-V of BLT capacitor were damaged by the polishing pressure which is one of the main factors to improve the CMP performance for BLT thin film; therefore, the lower polishing pressure must be selected for the good electrical characteristics although...
In this paper we present a improved method to reduce or eliminate a pop noise relates generally to digital -to-analog converters (DAC), when it is powered on or off.
This paper describes techniques and methods used to realize a seventh order switched capacitor low pass filter in SIMOX technology. The filter has bessel characteristic and a 3dB-bandwidth of 20Hz at a clock frequency of 100kHz. Special design of transistors and transmission gates results in drastically reduced leakage currents. The power supply voltage is 10V. The temperature range is extended up...
A short term analogue memory is described. It is based on a well-known sample-hold topology in which leakage currents have been minimized partly by circuit design and partly by layout techniques. Measurements on a test chip implemented in a standard 2.4 micron analogue CMOS process show a droop rate of 0.075mV per second with a 1pF hold capacitor. This is equivalent to a retention time of approximately...
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