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In this modern technology era, in System on Chip (SoC) design, performance of processing units in computer is always on demand. By having hardware accelerators in computer system, core processor can offload task to it and this creates parallel execution to improve the processing speed. One of the functional blocks that are crucial in Hardware Accelerator's design is Storage Unit, which is used to...
Traditionally, common processor augmentation solutions have involved the addition of coprocessors or the datapath integration of custom instructions within extensible processors as Instruction Set Extensions (ISE). Rarely is the hybrid option of using both techniques explored. Much research already exists concerning the identification and selection of custom hardware blocks from hardware/software...
3-Dimensional Networks-on-Chip (3D NoC) are emerging as a promising solution to handle efficiently interconnects' complexity in 3D System-on-Chip (SoC). This paper presents a new router that enables gains in terms of throughput and latency compared to classic 3D mesh the in case of large NoCs. The proposed router is hierarchical since it is composed of 2 totally decoupled modules: one for inter-layer...
Nowadays, service connectivity adaptation grows to be one of the most important topic in SOC (Service Oriented Computing). Due to the increasing in accessing the business processes of the information systems, there is a lot of traffic to a specific part of its business logic (BL) that causes Bottlenecked. To solve this traffic problem, we need to adapt the business logic and the services connectivity...
On-chip communication architecture plays an important role in determining the overall performance of the system-on-chip (SoC) design. In the resource sharing mechanism of SoC, the communication architecture should be flexible to offer high performance over a wide range of traffic. The low priority components may suffer from starvation, while high priority components may have large latency. The conventional...
Software defined radio (SDR) is gaining much attention in many application fields, e.g. satellite communication (SATCOM). In this paper, the requirements of SDR architecture for SATCOM application are discussed and a novel network on chip (NoC) architecture proposal are presented in order to achieve these requirements. Compared with several common NoC architectures, the proposed NoC can reduce the...
We describe a stochastic circuit generator that can be used to automatically create benchmark circuits for use in FPGA architecture studies. The circuits consist of a hierarchy of interconnected modules, reflecting the structure of circuits designed using a system-on-chip design flow. Within each level of hierarchy, modules can be connected in a bus, star, or dataflow configuration. Our circuit generator...
Recent development in System-on-Chip(SOC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. Thus, the proposed scheme supports the various memory test algorithms to test different types of memory modules in SOC. Moreover, it is able to...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
The challenges of deriving early-adopter competitive advantage, even with fabless access to process technology, through leveraging features offered by the advanced, and possibly disruptive, process technologies in real SoC products, are outlined. A structured methodology for addressing these challenges, and bridging the gap between process and design, sufficiently early in the development cycle to...
System architects working on SoC design have traditionally been hampered by the lack of a cohesive methodology for architecture evaluation and co-verification of hardware and software. This paper focuses on a comprehensive analysis framework providing platform assembly facilities, system analysis tools, enhanced traffic model and SystemC TLM IP. This framework has been intensively used to design and...
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