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The continuous transistor scaling and extremely lower power constraints in modern VLSI chips can potentially supersede the benefits of the technology shrinking due to reliability issues. Due to external aggression factors, e.g., radiation and temperature gradients, the CMOS devices flawless functioning cannot be guaranteed any more. Thus, design time Integrated Circuits (ICs) reliability assessment...
As CMOS technology advances to nano-scale devices, the performance of logic integrated circuits becomes a focal point in current literatures. The circuit's performance measured based on its reliability is not only depending on its gate error probability, p, but it also depends on the architecture of that circuit. Thus, this drives a need to measure and evaluate reliability values for different architectures...
The reliability of digital circuits is greatly distorted as the VLSI design cycle enters into nanoscale arena. In the past, the inputs of digital circuits were considered deterministic but shifting of transistor technology into nanoscale dimensions has made their behaviour totally probabilistic. The reason is that logic level voltages suffer from a number of fluctuations due to the effect of signal...
We elaborated a new ultra low-power nanometer circuit design methodology by introducing statistical fluctuations in advanced technology nodes as noise sources causing computational errors. The modeling is performed on sub-50 nm technology node to create a statistical performance metric. The relationship between the probability of error and the circuit noise for a variety of different configurations...
We present a novel trigonometry-based probability calculation (TPC) method for analyzing circuit behavior and reliability in the presence of errors that occur with extremely low probability. Signal and error probabilities are represented by trigonometric functions controlled by their corresponding angles. By combining trigonometric identities and Taylor expansions, the effect of an error at a particular...
Markov chains with Labelled Transitions can be used to generate test cases in a model-based approach. These test cases are generated by random walks on the model according to probabilities associated with transitions. When these probabilities correspond to a usage profile, reliability may be estimated. However, in early stages of development, such probabilities are not easy to determine, thus default...
As the sizes of (nano) device are aggressively scaled deep towards the nanometer regime, the design and manufacturing of future nano-circuits will become extremely complex and inevitably introduce more defects and their functioning will be adversely affected by transient faults. Therefore, accurately calculating the reliability of future designs will become a very important factor for nano-circuit...
A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and the gate error probability and produces the error probability at the output of the gate. The presented model uses the Boolean difference calculus and can be applied to the problem of calculating the error probability at the...
This paper proposes a new reliability model for individual single-electron tunneling (SET) logic gates. We study a typical SET logic gate (2-input NAND gate) to quantitatively associate the gate reliability with actual process variations as well as input patterns. This model can be used in future CAD tools to analyze the reliability of SET-based digital logic circuits.
Reliability is a crucial issue in nanoscale devices including both CMOS (beyond 22 nm) and non-CMOS. Devices in this regime tend to be more prone to errors due to thermal effects creating uncertainty in device characteristics. The transient nature of these errors commands the need for a probabilistic model that can represent the inherent circuit logic and can measure the errors. In sequential logic...
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