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High-level synthesis for FPGA designs (FPGA-HLS) is recently required in various applications. Since wire delays are becoming a design bottleneck in FPGA, we need to handle interconnection delays and clock skews in FPGA-HLS flow. In this paper, we propose an FPGA-HLS algorithm optimizing critical path with interconnection-delay and clock-skew consideration. By utilizing HDR architecture, we floorplan...
Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-aware HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing...
We have designed a multichannel readout board to replace the old A-RX board of the LHCb TELL1, which is able to readout and process up to 8 BEETLE chips. We doubled the number of channels and the sampling speed of the old A-RX replacing the ADC with new serial converters and we added a powerful Kintex-7 FPGA to pre-process the data. Each board is able to readout 1024 channels simultaneously at the...
In this paper, an efficient packing algorithm based on constraint satisfaction problem technique is proposed for contemporary FPGA CLB architecture. No matter how complex the architecture is, there are a limited number of patterns, which can implement all functionalities of FPGA CLB logic. All the patterns are pre-designed and known as reference circuits. The proposed algorithm then matches the reference...
Computationally intensive problems can be represented with data-flow graphs and automatically transformed to locally controlled floating-point units via partitioning. In theory the lack of global control signals enables high performance implementation however placing and routing of the partitioned circuits are not trivial. In practice to create a high performance implementation the clusters should...
This paper addresses the design of the mapping tool used for the FPGA application implementation in our SRAM-based FPGAs fabricated in a 0.5 micron SOI-CMOS process. Comparing with the existing mapping tools from academia, we propose several techniques of packing and clustering to improve the technology mapping. The proposed algorithms provide a closer matching of the user logic netlist with the underlining...
Multi-FPGA systems (MFS's) represent a promising technology for various applications, such as the implementation of supercomputers and parallel and computational intensive emulation systems. On the other hand, dynamic reconfigurability expands the possibilities of traditional FPGAs by providing them the capability of adapting their functionality while still running to cope with runtime environment...
In recent years, pre-fabricated design styles grow up rapidly to amortize the mask cost. However, the interconnection delay of the pre-fabricated design styles slows down the circuit performance due to the high capacitive load. In this paper, we propose a technique to insert dual-rail wires for pre-fabricated design styles. Furthermore, we propose an effective dual-rail insertion algorithm to reduce...
This paper presents a new parallel processing wire routing machine, which finds a quasi-minimum Steiner tree for multi-point connections in a VLSI chip. A hardware implementation with concurrent time-multiplexed wavefront propagation from all terminals of a net is described. The new design requires fewer clock cycles to find the shortest path than the existing parallel routing algorithms. The time-multiplexed...
FPGA placement algorithms have stricter location constraints compared to normal ASIC placers. For large circuits, designers often start by using a best local solution and iterate until a reasonable global solution is attained, with optimization criteria such as minimum delay, area and power. This paper presents a modified greedy algorithm for placing Xilinx FPGA blocks, specifically designed for large...
This paper proposes a novel fault tolerant algorithm for tolerating stuck-at-faults in digital circuits. We consider in this paper single stuck-at type faults, occurring either at a gate input or at a gate output. A stuck-at-fault may adversely affect on the functionality of the user implemented design. A novel fault tolerant design based on hardware redundancy (replication) is presented here for...
Nowadays, FPGA architecture has been improved rapidly, and more and more hard structures are integrated on heterogeneous FPGA chips. RTL technology mapping is one of methods to solve the problem of making use of those hard structures efficiently. However, the traditional RTL mapping tools can not do optimization on the delay on interconnect wires which can not be ignored in the current integrated...
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high supply voltage (high-Vdd) or a low supply voltage (low-Vdd). We carry out the clustering procedure with the guarantee that the delay of the circuit under the general delay model is optimal, and in the meantime, logic blocks...
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