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In Systems Biology, Boolean models are gaining popularity in modeling and analysis of qualitative dynamics of gene regulatory mechanisms. With the development of advanced high-throughput technologies, the availability of experimental data on gene-gene, gene-protein interactions is ever increasing. Consequently, modern Boolean models are increasing in size and complexity. Software simulation of Boolean...
In this work, we present a modular software subsystem that exposes a set of APIs for supporting the automation of a set of design choices in the synthesis of a hardware accelerator by a proprietary FPGA toolchain. We model the subsystem around Vivado, Xilinx's proprietary FPGA toolchain, in order to provide a finer grained control on the toolchain's features with respect to the standard .tcl interface...
FPGA devices allows designer to implement complex digital architectures that involve hardware and software components. Because of the different features of hardware and software design, diverse mechanisms and tools have been proposed for debugging and verification of architectures implemented on FPGA devices. Bus level transactions and data processing algorithms are usually difficult to manage together...
This work examines the feasibility of using Ethernet-based time transfer methods based on White Rabbit technology to discipline all the clock domains of a networked data acquisition system (DAQ). Existing systems provide synchronization capabilities, albeit the performance achieved is often not accurate enough for scientific infrastructures and Smart Grid applications requiring frequency coherent...
Using software defined radio (SDR) systems for time and frequency metrology offers the possibility to perform measurements with high precision. Common off the shelf SDR systems are not always a good match for metrological applications as they do not generally offer ways to lock the local sampling clock to an external source or have lax noise requirements. We have built a flexible platform for SDR...
This paper presents a versatile tool for development, control and testing of power electronics converters. In the last decade, many different expensive off-the-shelf tools for rapid prototyping and testing have been developed and commercialised by few market players. Recently, the increasing diffusion of low cost, Do It Yourself targeted development tools gained market shares previously controlled...
In access-network-chip testing and verification, problems occur mostly on I2C control interface because of its complicated protocol and high requirement on reliability, using an automated testing tool with simple operation and high testing coverage could ensure the quality of chip as well as shorten the chip development cycle. The paper designs an automated system based on 5SGXEA7N2F45C2 FPGA chip...
The template matching is an important technique used in pattern recognition. It aims at finding a given pattern within a frame sequence. Pearson's Correlation Coefficient (PCC) is widely used to evaluate the similarity of two images. This coefficient is computed for each image pixel, which entails a computationally very expensive process. This paper proposes an implementation of the template matching...
SAT is one of the most important basic problems of many areas of computer science and control science. SAT solvers are software or hardware to solve an SAT instance. In this paper, an instance-specified SAT solver was developed with FPGA, which implements the DPLL algorithm with our innovative random variable selection. Moreover, we also introduced an innovative tool-chain of our SAT solver, which...
Scan-path test, which is one of design-for-test techniques using a scan chain, can control and observe internal registers in an LSI chip. However, attackers can also use it to retrieve secret information from cipher circuits. Recently, scan-based attacks using a scan chain inside an LSI chip is reported which can restore secret information by analyzing the scan data during cryptographic processing...
This paper introduces a kind of virtual logic analyzer based on FPGA for hardware circuit and LabVIEW graphical language for the host computer software. It focuses on the integration of the hardware, and data processing by software. The results of specific tests show that the virtual instrument has the characteristics of functional modularization, friendly interface, easy maintenance, lower cost and...
This paper reports our implementation of an experimental system to generate DB-T2 signal based on a commercial FPGA (Field Programmable Gate Array) board with additional instruments. The baseband OFDM (Orthogonal Frequency Division Multiplexing) samples are computed offline via a C program. The OFDM samples are stored in an SD card for the FPGA board to read. The FPGA board converts the digital samples...
High-Level Synthesis (HLS) has opened an opportunity for software programmers to target FPGA more rapidly. When developing HLS tools, tests are desirable to ensure their function, reliability and performance. When modifications are applied to a tool, Non- Regression Test (NRT) asserts that the changes have intended effect while Regression Test (RT) verifies that the tool still performs correctly without...
In high-performance computing systems, each computing node communicates via a high-speed serial bus to ensure sufficient data transfer bandwidth. However, each computing node of different bus protocols is very difficult to communicate directly, which is not conducive to the extensibility of HPC (High performance computing) clusters. In this paper, we propose UPI, a inter-node communication interface...
Field Programmable Gate Arrays (FPGAs) have been extensively used in accelerating applications in many digital domains, examples include image and signal processing. These applications have been abundantly tested in high level languages like C, C++ and Matlab programming. Many standard libraries exist for image processing applications like OpenCV for end to end solutions. Applications centered around...
In this paper, we present a novel co-designed architecture for high throughput database query processing. It consists of a highly configurable FPGA-based filter chain with arithmetic operation support and an alignment unit. This feeds the filtered data directly and in a cache-optimized way to embedded processors which are responsible for joining tables and post processing. High throughput interfaces...
Computer designers rely upon near-cycle-accurate microarchitectural simulators to explore the design space of new systems. Hybrid simulators which offload simulation work onto FPGAs (also known as FAME simulators) can overcome the speed limitations of software-only simulators. However such simulators must be automatically synthesized or the time to design them becomes prohibitive. Previous work has...
Local triple modular redundancy (LTMR) is often the first choice to harden a flash-based FPGA application against soft errors in space. In this work, we compare parity-based error detection with software-based retry, and LTMR on a reference architecture regarding maximum frequency, area overhead and processing time. Our results show that our solution based on parity-based error-detection saves from...
In order to realize high-speed sampling, converting and real-time transmission in superlattice random signal processing, a high-speed true random number acquisition system based on semiconductor superlattice was designed. This paper introduced the overall system, the design of hardware, the implementation of software and the speed of transmission. The testing results of this system demonstrate that...
Radar signal simulator play a key role in radar debugging, performance evaluation and equipment maintenance. The large bandwidth, high power transmitter is always a hot research area in radar signal. The radar signal simulator used as the signal source, can generate multi-channel arbitrary waveform by software programming which can meet the requirement of real-time signal output. With the development...
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