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A 1.2-V 42.3-μW three-stage amplifier capable of driving 0.5-to-15-nF capacitive load is proposed. By removing the inner Miller capacitor and adopting cascode Miller compensation in the outer feedback loop, the complex-pole frequency is extended effectively and the size of the compensation capacitors is reduced. Moreover, the Q-factor is reduced by paralleling a small Miller capacitor to the cascode...
A loop stability compensation technique for continuous-time common-mode feedback (CMFB) circuits is presented. A Miller capacitor and nulling resistor in the compensation network provide a reliable and stable operation of the fully-differential operational amplifier without any performance degradation. The amplifier is designed in a 130 nm CMOS technology, achieves simulated performance of 57 dB open...
This paper studies the methodology of power integrity (PI) analysis for high speed printed circuit board (PCB) design. This involves the analysis of AC and DC characteristic of the PCB, and also the loop stability of the switch mode voltage source. Besides this, the best practices of designing a power rail with excellent fidelity are discussed in detail in this paper. The basic theory of operation...
A power-efficient frequency compensation topology for three-stage transconductance amplifiers is presented in this paper. Stability analysis and design equations are carried out based on the small-signal model. Unlike many recently reported solutions, the proposed architecture do not rely upon parasitic and/or pole-zero cancellation, thus providing a more robust design. As an example, the proposed...
This second part follows a first part where a background study and the implementation process of fractional order systems were presented. In this part, the results of the test bench are shown. Some uncertainties, related mainly to the parametric effects, as the components tolerance, are also presented in order to study the stability and the robustness of the system toward these variations. The results...
In this first part, we present a background study of the fractional order system and the way to synthesize and implement those systems in the electrical domain by means of resistors and capacitors. The electrical test bench used to implement this fractional order system of the first kind is shown as well as two different arrangements. The first one is based on a fractional order system while the second...
This work deals with the design and analysis of a controller for a shunt active power filter. The design is based on combined feedforward and feedback actions, the last using odd-harmonic repetitive control, and aims at obtaining good closed-loop performance in spite of the possible frequency variations that may occur in the electrical network. As these changes affect the performance of the controller,...
This paper presents a modified single Miller capacitor feed forward compensation design for regulators resulting in a linear LDO (low dropout) regulator whose performance is independent of the off-chip capacitor and its ESR (equivalent series resistor). The proposed compensation method ensures the stability of the feedback loop and the sufficient phase margin of the LDO regulator. The proposed design...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
This paper presents the design considerations for a stacked transistor topology for power amplifier design. A HBT is used to show at 1 GHz the effect of bias, device size, and matching, including interstage matching, which has had no beneficial effect so far. Most important is the base capacitor termination of the top transistors.
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