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In this paper we present a solar harvester test chip, realized to characterize several integrated solar cell structures, gathering the information required to design a complete power management system for handling the harvested energy. In particular, we realized photodiodes with three different geometries of the p-diffusion, and three different dimensions of the n-well. The chip is realized in a 0...
In this paper, a low-power high-performance logic style for low-voltage CMOS technologies is presented. The style is based on modifying a high-speed yet low-power logic family called feedthrough logic (FTL) style which has been previously proposed in the literature. The proposed style which is called parallel FTL (PFTL) overcomes the shortcoming of the FTL for low-voltage applications. To assess the...
An algorithm is presented to extract device mismatch parameters for high voltage transistors. The mismatch parameters are determined in two steps. The device mismatch for the threshold voltage, the gain factor and the mobility reduction are extracted from a sensitivity model in saturation, whereas the extraction of the drift-resistance mismatch is carried out based on a MOS transistor model in the...
The ESD robustness of LATID (Large Angle Tilted Implanted Drain) MOSFET for I/O drivers is evaluated and found inadequate for deep submicron 5 V CMOS technology. Alternative drain structures are examined and reported to meet the ESD and other criteria. An additional phosphorous implant that creates a LATID/DDD (Double Diffused Drain) structure meets all ESD and device criteria.<<ETX>>
Two specific issues impacting the eventual application of optical interconnection in full-wafer systems are addressed. The first issue is growth of GaAs semiconductor regions within a silicon wafer scale integration (WSI) or multichip module (MCM) substrate containing high performance silicon CMOS circuitry, in order to cointegrate optical and silicon VLSI devices. The second concerns the addition...
As CMOS scaling is approaching 0.1 mu m channel length, the authors examine a number of key device and technology issues which will ultimately determine the limit of room temperature scaling. High speed and high transconductance (750 mS/mm for n, 400 mS/mm for p) sub-0.1 mu m nMOSFET and pMOSFET devices have recently been demonstrated. P/sup +/ polysilicon gate was used on 35 AA gate oxide without...
A novel 'decoupled C-V' technique is proposed to characterize the channel and overlap capacitances of miniaturized MOSFET's. This method successfully decouples channel capacitance from overlap capacitance in submicron CMOS devices. The intrinsic channel capacitance can be well modeled by the quasi-static C-V theory. It allows the accurate determination of the effective channel length and effective...
The simple approach of thermal oxide capped poly refill trench isolation (Rung et al., 1982) is studied with regard to the impact of cap oxide thickness, trench wall thermal oxide thickness, and trench depth on MOSFET and isolation characteristics. It is shown that an increase of cap oxide thickness (t/sub ox/) from 600 to 2000 AA eliminates subthreshold double-hump phenomena, improves isolation V/sub...
Complementary 0.15 mu m MOSFETs and double-diffused lateral BJTs have been successfully integrated in a 10-mask CBiCMOS process, by utilizing the process simplifications that are unique to thin-film SOI. The CMOS devices are built in a SIMOX silicon layer of intermediate thickness (130 nm), leading to nearly-fully-depleted (NFD) characteristics. Excellent short-channel behavior is observed down to...
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