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This paper presents an efficient design method used to implement high performance multi-mode memory controllers which fits different applications with different demands. The proposed design method is based on the use of dynamic partial reconfiguration (DPR) to commute from mode to another using time-multiplexing on the same chip region to save considerable area and enable usage of low-cost FPGAs....
Poor data locality in high-speed networks leads to more memory accesses of connection management, which limits the throughput performance. In view of the above problem, this paper analyzed the process of connection management and access in detail, and put forward the efficient connection management solution to improve throughput on FPGA platform. This solution takes full advantage of the structural...
With the development of embedded systems, more and more applications require large and high speed memory. The FPGA-based solution also faces the same demand. Design and realization of an external storage with large capacity and high throughput in the FPGA-based embedded system is becoming a challenge. To satisfy the practical requirement, a DDR2 controller design is proposed, which efficiently and...
High speed Internet routers and switches require fast packet buffer to hold packets during times of congestion. These buffers usually use a memory hierarchy that consist of expensive but fast SRAM and cheap but slow DRAM to meet both, speed and capacity requirements. A challenge building these packet buffers is to provide deterministic bandwidth guarantee under any traffic condition. We propose a...
This paper presents a design that realizes a dual-channel Data Record Card which achieves 33 MB/s data transfer rate and 4 GB capacity per channel with CF Card and SDRAM. According to the characteristics of data transfer with CF Card, an advanced data transfer method is provided, which reduces the requirements of memory resources in FPGA without influencing the data transfer rate. And it realizes...
This paper analyzes possible performance improvement of streaming applications by the parallel computation platform of FPGAs. Software developers still are not familiar with the hardware implementation details of applications and will benefit from this analysis. First the available logic and memory resources of modern FPGAs like Xilinx's Virtex-5 and Virtex-6 devices are explored to determine how...
Since its release in 1998, the PXI industry standard has quickly developed in varieties of general industrial measurements and automation systems. In this paper, a kind of data acquisition architecture for multi-channel data acquisition systems based on PXI platforms is presented in detail. The proposed architecture model keeps a balanced equilibrium among complexity, speed, data storage memory, and...
Linear systems with Toeplitz coefficient matrices often appear in applied science problems. Systems of this form arise as a result of finite difference methods when applied to approximate differential equations with boundary conditions. The sparse structure of Toeplitz matrices lend themselves well to iterative algorithms, such as projection methods, and are favored techniques for solving large systems...
Previous full virtualization techniques are implemented in software without any hardware assist. In this paper, for the first time, we propose an advanced hardware assisted full virtualization architecture-Dynamic Binary Translation in DIMM (DBTIM). We integrate a reconfigurable dynamic binary translation chip into a DIMM. DBTIM could be inserted to the mainboard as a normal DIMM, hence easily making...
Boundary-scan testing is used to overcome many of the testability issues facing today's higher density designs. In the past, boundary-scan has been used successfully to perform interconnect testing between boundary-scan supporting devices. There has been an increased use of testing clusters of non-boundary-scan devices that are surrounded by boundary-scan access at the edge of the circuit both in...
DDR-SDRAM based data lookup techniques are evolving into a core technology for packet lookup applications for data network, benefitting from the features of high density, high bandwidth and low price of DDR memory products in the market. Our proposed DDR-SDRAM based lookup circuit is capable of achieving IP header lookup for network line-rates of up to 10 Gbps, providing a solution on high-performance...
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