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In this paper, an 8-bit (with 5-8bit mode selection), 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-μm CMOS process. In the 8-bit mode, measured effective...
A pipelined analog-to-digital converter (ADC) using an incomplete-settling-without-slewing technique is proposed and verified by SPICE simulations. Our analysis shows that operational amplifiers (opamps) in multi-bits stages can avoid slewing and linearly settle for whole period of amplification. If opamp does not experience slewing, the error caused by incomplete settling can be regarded as a constant...
This paper presents a 10-bit 40-MS/s pipelined ADC in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency...
In this paper, an 8-bit, 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-μm CMOS process. Simulated effective number of bits (ENOB) of the ADC is 7.09 with...
In this work, a low noise low power neural signal amplifier is presented. This amplifier consists of a first-order high pass filter and an OTA. We study the effect of using n-type MOSFET and p-type MOSFET in input stage of OTA, on its overall noise. Then two circuit schematic for overall amplifier is suggested. Finally, the simulation results of suggested amplifier are presented. The gain of amplifier...
This paper presents a new topology for a fully digitally programmable current-mode filter. The proposed scheme is based on the current conveyor cell in. The circuit is preferred for low power low voltage applications since it is based on CMOS inverters and op-amps only. The proposed circuit is employed to implement digitally variable capacitor for low cut off frequency filter design. The proposed...
This paper propose a suitable structure to increase the gain and speed of low-voltage amplifiers by means of modifying the first stage of the Folded-Cascode (FC) structure and exploiting class AB amplifier with active load at the second stage. In spite of the fact that cascode structures increase the output impedance, we make an extra pole in the transfer function of the network to raise the transconductance...
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