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The crossbar resistive random access memory (RRAM) has been studied extensively due to its low-power, low-cost, high density and nonvolatile characteristics. However, the dependence of RRAM performance parameters on temperature, from cell to array level, is less explored. Particularly, thin-film based RRAM that is integrated into 3D ICs is subject to severe thermal conditions. Hence, temperature dependence...
Today's explosive demand for data transfer is accelerating the development of non-volatile memory with even larger capacity and cheaper cost. Since the introduction of 3D technology in 2014 [1], V-NAND is believed to be a successful alternative to planar NAND and is quickly displacing planar NAND in the SSD market, due to its performance, reliability, and cost competitiveness. V-NAND has also eliminated...
Presented in this paper is a novel temperature sensor architecture in which we have been able to demonstrate a good temperature measurement accuracy and consistent part to part linearity. This architecture addresses the need for increasingly precise temperature sensors whether stand-alone or embedded within a standard mixed signal process. Also presented is the architectural principle implemented...
In this paper, we study the problem of resistance drift in an MLC Phase Change Memory (PCM) and propose a solution to circumvent its thermally-affected accelerated rate in 3D CMPs. Our scheme is based on the observation that instead of alleviating the problem of resistance drift by using large margins or error correction codes, the PCM read circuit can be reconfigured for tolerating most of the resistance...
We have proposed an integrated method to realize MLC PRAM at 45 nm technology node and beyond. It includes reset initialization, Toff skew write, and 2bit write to enhance write-and-verify speed, and 3-cell reference scheme to cope with cell variation due to resistance drift and temperature change. Based on the proposed methods, write throughput can be increased up to SLC level with robust read operation.
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
The present work aims at studying the cooling performance of a thermoelectric device that integrated with integrated heat spreader (IHS) on a flip-chip plastic ball grid array (FC-PBGA) package. The new thermoelectric device herein is fabricated on the metal substrates by flip-chip assembly process. Thermal performance of the new package was comprehensive studied. The thermal resistances of IHS with/without...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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