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This paper reports the analyses of two techniques for phase noise reduction in the CMOS Hartley oscillator circuit topology. Namely, the two techniques inductive degeneration and optimum current density are investigated with the objective of exploring the potential benefits in the mm-waves frequency range. The circuit sizing is carried out in 28 nm bulk CMOS technology. Overall, the analyses show...
In this paper, a novel digital post-correction method with real-time FPGA implementation is proposed to correct the distortion generated by high-speed analog-to-digital converters (ADCs). It is achieved by simplifying the dynamic deviation reduction-based Volterra series to form an accurate model to effectively compensate both static nonlinearities and memory effects. Both post-correction model generation...
In this paper the determination of the positions of surface plate electrodes on human trunk for measuring the breathing and heart rate by using the electrical bioimpedance is presented. The designed and implemented measurement device — electrode shirt — is described. The novelty of current work is incorporated into the solution of placing the large surface plate electrodes into the garment. Focus...
This paper presents a novel active phase shifter circuit topology based on LC all-pass lattice filter with variable inductors and capacitors within an amplifier. By tuning properly the inductance and capacitance of the filter it is possible to shift the input signal by the desired amount of phase from 0° to 180°. The preliminary design of a 60-GHz 8-phase phase shifter with phase resolution 22.5°...
Planar structures such as single microstrip Line (SML) and microstrip coupled line (MCL) are basic components in RF circuits and systems. Traditionally, analysis parameters of SML and MCL, an effective permittivity (εeff) and characteristic impedance (Zc), are obtained using piecewise empirical functions. The intervals boundaries depend on the line width to the substrate high ratio (w/h) value. In...
This paper reports the analyses of two techniques for phase noise reduction in the CMOS Colpitts oscillator circuit topology. Namely, the two techniques inductive degeneration and optimum current density are investigated with the objective of exploring the potential benefits in the mm-waves frequency range. The circuit sizing is carried out in 28 nm bulk CMOS technology. Overall, the analyses show...
A Bio-Impedance Signal Simulator (BISS) is developed based on the models of the impedance cardiography (ICG) and impedance respirography (IRG) signals. With the aim of imitating the real ICG and IRG phenomena, the ICG and IRG signals are modelled and combined with motion artefacts and Gaussian noise. The simulator allows the user to load different predefined human activity states such as resting,...
This paper presents an alternative architecture for a Monolithic IC Buried Zener-type voltage reference implemented on a 0.6μm BICMOS process. Low supply voltage, good power supply rejection, reduced process dependency, low Long Term Drift (LTD) with capability of an easy and effective Temperature Coefficient (TC) trim are all features of the presented architecture. Good simulated performance and...
This paper presents the results of the study aimed at evaluating the impact of the switching section on the design of a millimeter-wave system-on-chip Dicke radiometer for the space-based detection of solar flares. The radiometer operates at the frequency of 36.8 GHz and is expected to be implemented in a 0.25 μm SiGe BiCMOS technology by IHP, under Space evaluations. System analysis and circuit simulations...
This paper presents a novel approach to design and develop a wheeled mobile robot for education and research. A prototype differential wheels controlled mobile robot is developed using Tinkerforge building blocks. It has two independently controlled wheels at the back and one supporting wheel in the front. Tinkerforge building blocks supply a fast, sufficient and affordable solution to construct a...
This paper presents a millimeter-wave low noise amplifier designed in 65 nm bulk CMOS technology by using the technique of the transformer-based input integrated matching in cascode amplifiers. The proposed technique allows us to realize impedance matching to a 50 Ω source resistance by exploiting an integrated transformer. The measurement results show a S21 peak of 13.1 dB at 72 GHz, a 3-dB bandwidth...
Electricity companies will only allow customers to inject power into the grid network if the customer's system is in synch with both frequency and phase as the grid itself. This is normally achieved using a specialised machine sold by the energy provider. It may be possible to achieve this via low cost, low power nodes such as a Raspberry Pi, to synchronize frequency and phase as well as voltage and...
In this paper, optimisation algorithms are successfully applied to a number of antenna array beampattern synthesis problems — including, a Uniform Linear Array (ULA), a ULA with an inactive element, and a 2D Wireless Sensor Network (WSN) array. The algorithms presented include a Greedy Algorithm (GDA), a Metropolis Algorithm (MA), and a Genetic Algorithm (GA).
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