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In this work, we present a novel bit-cell which improves data stability in subthreshold SRAM operation. It consists of eight transistors, two of which cut off a positive feedback of cross-coupled inverters during the read access. In addition, the bit-cell keeps the noise-vulnerable data ‘low’ node voltage close to the ground level during the dummy-read operation, and thus producing near-ideal voltage...
Scaling of MOS technology creates new challenges to the SRAM circuit design, mainly leakage power and stability. A new seven transistor SRAM (7T) is proposed in this paper which eliminates the stability issues, reliable write and has a reduced cell area. Leakage current in proposed 7T SRAM cell without Super cut-off word lines is almost same as in 6T SRAM cell and proposed 7T SRAM cell with super...
In this paper, we designed a 9T SRAM cell using dual voltage threshold (DVT) and stacking effect. To achieve high density, low power and high performance, device scaling has been continuously done that result in increase in leakage power dissipation. At sub-micron technology, about 30% of total power dissipation is due to leakage power dissipation. The purpose of this paper is to analyze the Performance...
An area-efficient 4-port register file is presented for real-time microprocessors. Bitcell area efficiency is achieved with one-sided read operations and single-ended write operations together with an additional higher voltage source for write operations. High bitcell stability is maintained with one-sided read operations when the supply voltage is scaled down to 0.7V. Array-wide power savings are...
Wireless sensor network systems as supplied by Senceive are now totally accepted as a cost effective, precise and reliable tool for the condition monitoring of rail, geo-technical and structural assets. They are providing for remote monitoring of assets through the use of low cost, battery powered, high precision, self-configuring wireless sensor systems which can be readily installed with a minimum...
Static Random Access Memory (SRAM) is the most popular circuit which is used in all processors and occupies the considerable area of the chip. The total power consumption of circuit is largely dependent on power dissipated by memory. There were several efforts for reduction in power consumption such as Power Gated SRAM circuits and increasing virtual ground voltage. The previous techniques were capable...
A seven transistor (7T) static random-access memory (SRAM) cell with single-ended read and write operations is evaluated in this paper. The cell topology consists of a single bitline, a cross-coupled inverter pair with a transmission gate employed in the feedback path, and a bitline access transistor. Simulation results with 8 Kib SRAM arrays indicate up to 49.3% reduction in leakage currents, 42...
Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing supply voltage in scaled CMOS technologies. A selected set of novel seven-transistor (7T) and conventional six-transistor (6T) multi-threshold-voltage...
A new FinFET memory circuit technique based on asymmetrically gate underlap engineered bitline access transistors is proposed in this paper. The strengths of the asymmetrical bitline access transistors are weakened during read operations while enhanced during write operations as the direction of current flow is reversed. With the proposed asymmetrical six-FinFET SRAM cell, the read data stability...
In this work, we present a novel 8T SRAM cell that enhances the stability of built-in data storage elements. During a read operation, the proposed cell suppresses a noise-vulnerable ‘0’ node rising, and hence exhibiting near-ideal butterfly curve essential for robust SRAM bit-cell design. The cell itself bears an improved variability tolerance which gives much tight stability distribution across skewed...
Data stability is a primary concern in today's high performance memory circuits with deeply scaled transistors and power supply voltages. Recently proposed eight-transistor (8T) Static Random Access Memory (SRAM) cells offer enhanced data stability as compared to the conventional six-transistor (6T) SRAM cells by isolating the bitlines from data storage nodes during a read operation. Novel multi-threshold-voltage...
This paper introduces how SRAM cell stability changes with static noise margin during various operations while taking different parameters. The SNM changes various parameters of SRAM cell SNM varies during each cell operation. The cell ratio, pull up ratio is also play vital role in SRAM cell stability. We have analysis how SNM varies with the threshold voltage and supply voltage. We have taken various...
Data stability is a major concern in today's high performance memory circuits with deeply scaled transistors and power supply voltages. Multi-threshold-voltage (multi-Vt) nine-transistor (9T) Static Random Access Memory (SRAM) cells with enhanced data stability and superior overall electrical quality characteristics are presented in this paper. 9T SRAM cells eliminate the data disturbance by isolating...
Conventional six-transistor (6T) memory cell has an intrinsic data stability problem due to directly-accessed storage nodes during a read operation. The data stability issue becomes more severe with increasing variability and decreasing supply voltage in scaled CMOS technologies. Conventional techniques to enhance the data stability of 6T memory cells tend to sacrifice other important figures of merit,...
A new asymmetrical ground gated 7T SRAM circuit technique is presented in this paper to lower leakage currents and enhance noise immunity in idle memory banks. A novel write assist scheme is proposed to enhance write margin with the new memory circuit. The leakage power consumption is suppressed by up to 4.30× and the data stability is enhanced by up to 4.79× as compared with the previously published...
SRAM memory design in nanoscale regime has become increasingly challenging due to the reducing noise margins and increased sensitivity to threshold voltage variations. To overcome these challenges, different memory cells have been proposed for SRAMs with different transistor structures. These designs improve the cell stability in the subthreshold regime but suffer from bitline leakage noise, placing...
A new power gated 6T SRAM circuit is proposed in this paper to suppress leakage power consumption in data retention SLEEP mode. A new write assist circuitry is presented to enhance the write margin of the new power gated memory circuit. Design tradeoffs among data stability, power consumption, and write margin are evaluated with different SRAM circuits. The leakage power consumption is reduced by...
Ground bouncing noise produced during the sleep to active mode transitions is an important reliability concern in multi-domain Multi-Threshold CMOS (MTCMOS) integrated circuits. Ground bouncing noise, leakage power consumption, and data stability of MTCMOS flip-flops are evaluated in this paper. The effectiveness of different circuit techniques is discussed for achieving lower noise during the reactivation...
In this paper, it is given a new method of solving the fuzzy linear programming-the basic line algorithm. Compared with the simplex method in solving the fuzzy linear programming currently, the basic line algorithm not only has its advantages on both data stability and anti-cycle and so on, but also shows superior on reducing the solving steps and having no need to calculate the checking figures....
Various circuit topologies and FinFET technology options for implementing brute-force latches are explored in this paper. New low-power multi-threshold voltage (multi-Vth) FinFET brute force latches based on gate-drain/source overlap engineering and independent-gate bias are proposed. Different brute-force latches are characterized and compared for active mode power consumption, propagation delay,...
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