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Interface state density (Dit) at SiO2/4H-SiC interfaces is investigated using capacitance-voltage (C-V) characterization. Two different measurement methods for Dit determination (both C-V at different temperatures in the range of 80–300K and high frequency (HF) vs quasi static (QS) characteristics) have been used. A significant reduction of Dit is observed, almost one order of magnitude, after a post...
We investigated the electrical properties of highly-doped n-Si/n-Si and p-Si/p-Si junctions fabricated by using the surface activated bonding. Heights of potential barrier formed at the respective bonding interface were estimated by measuring dependence of their current-voltage characteristics on the ambient temperature. The heights of barrier were found to be varied due to annealing often the bonding...
The effect of roughness at the SiC/SiO2 interface on electrical properties of 4H-SiC MOS devices has been investigated. Variations in surface roughness were generated by annealing 4H-SiC samples at high temperatures (1550°C-1650°C) with or without a graphitic cap layer. Subsequently, gate oxides were grown on these surfaces for n-type MOS capacitors and n-channel MOSFETs were fabricated. Although...
We present a complete set of data on the surface passivation parameters of APCVD Al2O3 deposited with TEDA-TSB and H2O precursors at temperatures between 325 and 520 °C. Using measured values of the fixed charge Qf, and of the interface defect density Dit(E), electron capture cross-section σn(E) and hole capture cross-section σp(E) as a function of the energy within the bandgap E, we calculate surface...
While Al2O3 has been proven to provide an excellent level of surface passivation on all sorts of p-type doped silicon surfaces, the passivation mechanism of this layer and especially the influence of the post-deposition anneal on the Al2O3/Si interface properties is not yet completely understood. A great increase in the surface passivation is observed after a post-deposition anneal, i.e. a post-deposition...
In this paper, we have investigated bulk trap and interface trap density (Dit) caused by millisecond annealing (MSA) using gate current fluctuation (GCF) and charge pumping measurements. We show that the high energy flash lamp annealing (FLA) creates the GCF with a long duration time and it is critical issue to get a stable SRAM operation. FLA creates interface traps localized at the gate edge of...
We have developed an approach to perform “on the fly” electron spin resonance (OTF-ESR) measurements of negative bias temperature instability (NBTI) defect generation. This OTF-ESR approach allows for an atomic-scale identification of the defects involved in NBTI free of any recovery contamination. We demonstrate that, during NBTI stressing at elevated temperature and modest negative oxide bias, positively...
The SiO2/SiC interface limits optimum SiC MOSFET performance due to a high density of interface states (D????), which is reduced in devices that receive post-oxidation NO-annealing. Also, the interface state density in the 6H polytype is generally lower, approaching that of the NO treated 4H. In this work, interface states are investigated in both as-oxidized (AO) and NO-annealed (NO) MOS capacitors...
Photovoltaic and photoconductive properties of ultra-thin a-Si/SiO2 multilayers grown by PECVD and annealed at 1150degC were studied. A quantum yield greater than one is observed due to secondary carrier generation from interface trap states.
In this work MOS capacitors with anodic oxides (9 nm) were elaborated.The anodic silica films (SiO2) were produced by anodization of monocristalline silicon wafers in pure water in an electrolysis cell (P.T.F.E) at ambient temperature, with a constant current density of 20 muA/cm2. Film thickness increases linearly as a function of total charge during oxidation. The oxides are characterized by current-voltage...
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