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This paper discusses the influence of top-electrode (TE) and bottom-electrode (BE) materials on the resistive transition of sputter-deposited TiO2 films. The electronic characteristics of the TiO2 films are elucidated from the physical mechanism of resistive transition.
Properties of heterojunction diodes having polyvinyl pyrrolidone (PVP) on p-Si substrate are investigated. PVP layer has grown onto p type silicon substrate via the sol gel spin coating route @ 2000 rpm. The Front contacts have been thermally evaporated in vacuum onto the organic layer at low pressure of 10–6 T, having a diameter of 1.5 mm and a thickness around 250 ± 10 nm. In this research, the...
The upcoming 2011 general conference on weights and measures (CGPM) will consider a proposal to re-define the SI unit ampere by assigning a fixed value to the electron charge e, while simultaneously releasing the permeability of free space μ0 to become a measured parameter. This review provides the background to the proposed re-definition and describes research into electron pumps aimed at supporting...
We present a single wall carbon nanotube (SWCNT) based high frequency resonator fabricated using a novel process suitable for mass fabrication. The integration of the electrostatically actuated SWCNT into the silicon structure was achieved by a specially tailored fabrication process which is characterized by simplicity and compatibility with commonly used micro-machining processes. The fabrication...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
In this study, we fabricated in-plane thermoelectric micro-generators (4 mm times 4 mm) based on bismuth telluride thin films by using flash evaporation method. The thermoelectric properties of as-grown thin films are lower than those of bulk materials. Therefore the as-grown thin films were annealed in hydrogen at atmospheric pressure for 1 hour in a temperature range of 200 degC. to 400degC. By...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
An integrated Ge-on-SOI photo-detector based on secondary photo-conductivity is proposed and demonstrated. A 1 mW beam at 1.55 mum creates charge separation in the Ge thereby changing the resistivity of the underlying Silicon by ~3%.
This paper investigates the physics of 0.13 mum partially depleted SOI gated diodes through TLP measurements and TCAD simulations. The impact of gate length, well type, oxide thickness, gate to contact distance and presence of gate on ESD performance are evaluated and discussed. It is shown that the gate coupling effect decreases ESD performance.
We have measured electrical resistance R as function of temperature T in the range 2 % 20 K of severaL P implanted Silicon bolonmeters with the aim of optimize the characteristics of the bolometers. We have investigated the R(T) behavior of several samples obtaitned by varying implant conditions, depth profile and annealing.
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