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Formal verification utilizing symbolic computer algebra has demonstrated the ability to formally verify large Galois field arithmetic circuits and basic architectures of integer arithmetic circuits. The technique models the circuit as Gröbner basis polynomials and reduces the polynomial equation of the circuit specification wrt. the polynomials model. However, during the Gröbner basis reduction, the...
This paper presents a novel diagnosis and logic debugging method for gate-level arithmetic circuits. It detects logic bugs in a synthesized circuit caused by using a wrong gate ("gate replacement" error), which change the functionality of the circuit. The method is based on modeling the circuit in an algebraic domain and computing its algebraic "signature". The location and type...
The paper describes a method to derive a polynomial function computed by an arithmetic bit-level circuit. The circuit is modeled as a bit-level network composed of adders and logic gates and computation performed by the circuit is viewed as a flow of binary data through the network. The problem is cast as a Network Flow problem and solved using standard algebraic techniques. Extraction of the arithmetic...
With continuous scaling of transistors in each technology generation, NBTI and Process Variation (PV) have become very important silicon reliability problems for the micro processor industry. In this paper, we develop an analytical model to capture the impact of NBTI in the presence of PV for use in architecture simulations. We capture the following aspects in the model: i) variation in NBTI related...
The paper describes an algebraic approach to functional verification of arithmetic circuits specified at bit level. The circuit is represented as a network of half adders, full adders, and inverters, and modeled as a system of linear equations. The proof of functional correctness of the design is obtained by computing its algebraic signature using standard LP solver and comparing it with the reference...
The limitation of speed of modern computers in performing the arithmetic operations such as addition, subtraction and multiplication suffer from carry propagation delay. Carry free arithmetic operations can be achieved using a higher radix number system such as Quaternary Signed Digit (QSD). We proposed fast adders based on Quaternary signed digit number system. In QSD, each digit can be represented...
Digital CMOS circuits are praised because of their noise immunity. However, lowering power supply voltages and shrinking device sizes, in combination with the rising electromagnetic pollution, have made this statement no longer true. An accurate behavioral model is presented for the analog simulation of digital logic circuits. The model building is automated and scalable in the sense that it allows...
A kind of arithmetic and its implementation of bit-stream adder which can be used in digital signal processing were discussed in this paper. Compared with multi-bit adder, the bit-stream adder has the advantages of much simple structure and much small routing area. The ideal circuit model of the bit-stream adder was improved with a pipe line structure to make it work correctly in high frequency range...
Reliability analysis of digital circuits is becoming an important feature in the design process of nanoscale systems. Understanding the relations between circuit structure and its reliability allows the designer to implement some tradeoffs that can improve the resulting design. This work presents a probabilistic model that computes the reliability of combinational logic circuits relating to single...
We introduce a property of boolean functions, called transitivity which holds of integer, polynomial, and matrix products as well as of many interesting related computational problems. We show that the area of any circuit computing a transitive function grows quadratically with the circuit's maximum data-rate, expressed in bit/second. This result provides a precise analytic expression of an area-time...
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