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Digital computations and calculations is involved in every embedded and processing device, these devices has arithmetic logic unit or a special block to perform a desired operation, Addition can be one such operation, adders are most important and fundamental block used for Addition, Subtraction, Multiplication, Division, Address generation and so on, design and selection of adders for a embedded...
This paper presents a Reconfigurable Parallel Prefix Ling Adder. The proposed design can be partitioned to perform as one 16 bit, two 8 bit and four 4 bit adders. We also propose a new architecture for Enhanced Flagged Binary Adder (EFBA) designs which reduces the delay of operation considerably. The new adders are, therefore, modifications of conventional Reconfigurable Carry Lookahead Adder (CLA)...
Parallel-prefix computation provides a highly efficient solution to binary addition problem. This paper proposes an advanced design based on parallel-prefix Ling adder. In order to further improve the Ling adder's performance, the preprocessing block and carry propagation block are all optimized to reduce the delay path for sum generation. Experimental results indicate that the proposed adder has...
The limitation of speed of modern computers in performing the arithmetic operations such as addition, subtraction and multiplication suffer from carry propagation delay. Carry free arithmetic operations can be achieved using a higher radix number system such as Quaternary Signed Digit (QSD). We proposed fast adders based on Quaternary signed digit number system. In QSD, each digit can be represented...
A methodology for energy-delay optimization of digital circuits is presented. This methodology is applied to minimizing the delay of representative carry-lookahead adders under energy constraints. Impact of various design choices, including the carry-lookahead tree structure and logic style, are analyzed in the energy-delay space and verified through optimization. The result of the optimization is...
A kind of arithmetic and its implementation of bit-stream adder which can be used in digital signal processing were discussed in this paper. Compared with multi-bit adder, the bit-stream adder has the advantages of much simple structure and much small routing area. The ideal circuit model of the bit-stream adder was improved with a pipe line structure to make it work correctly in high frequency range...
Fast Fourier Transform (FFT) is the most basic and essential part of Software Defined Radio (SDR). Therefore, designing regular, reconfigurable, modular and low hardware complexity FFT computation block is very important. A single FFT block should be configurable for varying length FFT computation and also for computation of different transforms like DCT, DST etc. In this paper, the authors analyze...
This paper compares the three simplest SRT division methods by using them to design a divider that produces four quotient bits per cycle (radix 16). The three methods are distinguished by the number of bits found per stage of quotient selection logic: (a) one bit per stage (radix 2) with quotient digits chosen from the set {−1, 0, 1} (b) two bits per stage (radix 4) with quotient digits {−2, −1, 0,...
We introduce a property of boolean functions, called transitivity which holds of integer, polynomial, and matrix products as well as of many interesting related computational problems. We show that the area of any circuit computing a transitive function grows quadratically with the circuit's maximum data-rate, expressed in bit/second. This result provides a precise analytic expression of an area-time...
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