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Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of the super-chip are described. In addition, the reliability challenges such as the mechanical stress/strain and Cu contamination are discussed. Cu TSVs with the diameter of 20-μm induced the maximum compressive stress of ∼1 GPa at the Si substrate adjacent to them after annealed at 300°C. Mechanical strain/stress...
Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of super-chip are described. In addition, reliability issues in these 3D LSIs such as mechanical stresses induced by through-silicon vias (TSVs) and metal microbumps and Cu contamination in thinned wafers are discussed. Cu TSVs with the diameter of 20μm induced the maximum compressive stress of ~1 GPa at the...
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