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As the technology scales toward deeper submicron, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on-chip...
This paper presents a built-in self-test (BIST) system for Low-Dropout Regulators (LDO). Since the LDO is a closed-loop system, stability is a very important but oft-untested parameter for embedded LDOs. The proposed BIST system can measure stability-related parameters by performing cross correlation between an input pattern mimicking noise in the form of Pseudo Random Binary Sequence (PRBS) and the...
Increasing data set sizes motivate for a shift of focus from computation-centric systems to data-centric systems, where data movement is treated as a first-class optimization metric. An example of this emerging paradigm is in-situ computing in largescale computing systems. Observing that data movement costs are increasing at an exponential rate even at a node level (as a node itself is fast-becoming...
Recently, architectures with scratchpad memory are gaining popularity. These architectures consist of low bandwidth, large capacity DRAM and high bandwidth, user addressable small capacity scratchpad. Existing algorithms must be redesigned to take advantage of the high bandwidth while overcoming the constraint on capacity of scratchpad. In this paper, we propose an optimized edge-centric graph processing...
In this paper, design of a novel Network on Chip (NoC) structure and its integration with Reliable Reconfigurable Real Time Operating System (R3TOS) are presented. NoC has been recently identified as a scalable communication paradigm to avoid the communication bottleneck in bus based communications. Dynamically Reconfigurable Field Programmable Gate Array (FPGA)s are particularly suited for applications...
Sparse Matrix-Vector multiplication (SpMV) is a fundamental kernel for many scientific and engineering applications. However, SpMV performance and efficiency are poor on commercial of-the-shelf (COTS) architectures, specially when the data size exceeds on-chip memory or last level cache (LLC). In this work we present an algorithm co-optimized hardware accelerator for large SpMV problems. We start...
Novel applications demand computational resources that are provided by multiprocessor systems-on-chip (MPSoCs). At the same time, they increasingly process sensitive data and incorporate security-relevant functions like encryption or authentication. This paper discusses the implications of the MPSoC technology on security. It provides an overview of hardware-oriented techniques to enhance security...
The LEON series of processors has enabled space missions during the two past decades. This paper discusses the past, present and future of the LEON series of SPARC 32-bit space-grade microprocessors and system-on-chip devices.
The expanding use of deep learning algorithms causes the demands for accelerating neural network (NN) signal processing. For the NN processing, in-memory computation is desired, in which expensive data transfer can be eliminated. In reflection of recently proposed binary neural networks (BNNs), which can reduce the computation resource and area requirements, we designed an in-memory BNN signal processor...
To achieve a high performance of a system on chip design we should focus on a faster chip communication architecture based on different arbitration scheme. Where all master requests are having different priority. So designing the arbiter having ability to perform in worst corner cases. This paper is introduction to a modified dynamic bus arbiter based on fuzzy logic for a system on chip design architecture...
With the increase of CMP (Chip-Multiprocessor) scale, moving data to computation on chip becomes more expensive. Accordingly, moving computation to data has potential to improve efficiency. We propose an in-place computation co-design of many-simple-core CMP for irregular applications. The computing paradigm is that an application's critical irregular data (or part of them) is partitioned into on-chip...
Emerging nanodevices such as resistive memories are being considered for hardware realizations of a variety of artificial neural networks (ANNs), including highly promising online variants of the learning approaches known as reservoir computing (RC) and the extreme learning machine (ELM). We propose an RC/ELM inspired learning system built with nanosynapses that performs both on-chip projection and...
In order to meet the significant challenges in future MPSoCs they need be become more adaptive and autonomous. We argue that a self-aware MPSoC can efficiently manage itself even in the presence of aging, varying application demands, functional and non-functional aberrations, and thus achieve a high level of adaption and autonomy. We review CPSoC as an exemplar of a self-aware MPSoC and demonstrate...
Doing early design space exploration for manycore architectures is a challenge, all the more when the focus is on complex coherence protocols. Implementing such protocols in realistic simulation models is costly both in modelling effort and execution time. We propose a trace-driven method to accurately compare cache coherence protocols while keeping cache modelling at a high level of abstraction....
Recurrent Neural Networks (RNNs) have the ability to retain memory and learn from data sequences, which are fundamental for real-time applications. RNN computations offer limited data reuse, which leads to high data traffic. This translates into high off-chip memory bandwidth or large internal storage requirement to achieve high performance. Exploiting parallelism in RNN computations are bounded by...
The interest for more digital functionality in the readout circuits for imagers is growing rapidly. Similarly, there are advantages to having the pixel pitch smaller from visible to long wave IR. The front end is the dominant source of electronic noise for an in-pixel digital design. Limiting the real estate considerably would force the design to smaller feature size, which may worsen the random telegraph...
Cognitive computing describes “systems that learn at scale, reason with purpose, and interact with humans naturally” [1]. In this paper, we review our work towards enabling “next generation” cognitive computing using neuromorphic computational schemes that could potentially outperform present-day CPUs and GPUs. Here we use large arrays of Resistive Non-Volatile Memories (NVM) with device conductance...
Deep learning is becoming increasingly popular for a wide variety of applications including object detection, classification, semantic segmentation and natural language processing. Convolutional neural networks (CNNs) are a type of deep neural network that achieve high accuracy for these tasks. CNNs are hierarchical mathematical models comprising billions of operations to produce an output. The high...
Bilateral filtering (BLF) and median filtering (MF) are key components in many applications. As the image resolution grows rapidly, implementation of efficient filtering is highly demanded. In this paper, we present a unified VLSI architecture that is able to compute both kinds of filters for 4k2k videos at 30fps. One feature of this design is that we leverage an emerging layer-based algorithm for...
The paper deals with theoretical and practical prerequisites for the systems-on-chip design intended for measurement, processing and output of different kinds of heterogeneous signals. Some problems concerning the basic structure and architecture of these heterogeneous SOCs are investigated, as well as their possible application areas, features and preferences of the used heterogeneous components...
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