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Network-on-Chip (NoC) with wireless interconnects is one of the potential solutions to overcome limitations of conventional NoC architectures over far-apart communications in multicore systems. Detailed investigations of Wireless NoC (WNoC) highlight their many benefits. But, idle-state power consumption associated with WI interfaces and routers is significantly high. To reduce the idle-state power...
In recent years, designing specialized manycore heterogeneous architectures for deep learning kernels has become an area of great interest. However, the typical on-chip communication infrastructures employed on conventional manycore platforms are unable to handle both CPU and GPU communication requirements efficiently. Hence, in this paper, our aim is to enhance the performance of heterogeneous manycore...
Starting from the application perspective, this paper addresses on the needs for sensor node architecture, wireless communication, security and infrastructure for IoT.
Starting from the application perspective, this paper addresses on the needs for sensor node architecture, wireless communication, security and infrastructure for IoT.
Due to high latency and high power consumption in long hops between operational cores of NoCs, the performance of such architectures has been limited. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless Network-on-Chip (WNoC) has been emerged. Employing wireless communication links between cores, the new technology has reasonably increased...
The advances in semiconductor technology allow us to integrate a number of processing cores on a single chip or a single package. These many-core processors are expected to boost a wide range of applications from high-performance computing, cyber-physical computing, cloud, and big data processing. This tutorial first introduces recent many-core processors and then focuses on fundamental technologies...
Wireless communications have been one of the main forces behind the growth of microelectronics industry for the past two decades [1]. In fact, the continuous technological advance in the field of wireless communications has required the design and implementation of increasingly complex Systems-on-Chip (SoCs) to cope with the higher complexity of algorithms/communication protocols. Furthermore, in...
The Network-on-Chip (NoC) paradigm is used as a scalable interconnection infrastructure for multi-core chips. To enhance the performance of conventional interconnect-based multi-core chips, on-chip wireless interconnect has emerged as a radically different technology. However, this emerging interconnect paradigm imposes significant challenges pertaining to reliable integration and design. In this...
The following topics are dealt with: digital content; digital life; e-learning; Web service; HCI; information security; mobile computing; wireless communication; vehicular technology; image processing; computer graphics; multimedia technologies; computer architecture; SoC; embedded systems; artificial intelligence; knowledge discovery; fuzzy systems; computer networks; Web technologies; biomedical...
We propose a programmable heterogeneous multi-processor system-on-chip (MPSoC) platform architecture for flexible radio processing that aims at striking a balance between performance (as provided by ASICs) and flexibility (as provided by SDR). Based on a novel hardware-oriented Virtual Flow Pipelining (VFP) framework, the key highlights of this solution are a simple task-level programming model for...
This paper presents a single chip VLSI architecture of wireless image sensor node, which is constituted by an enhanced embedded 8051 microcontroller, a CMOS camera interface and hardware accelerators. The algorithms and control flows of the IEEE 802.15.4 MAC layer are accelerated by hardware, results in 45% less code size compared with the conventional software stack. An innovated CFA preprocessing...
We propose an architecture designed to connect two MACs at the MAC-PHY Interface (MPI) for UWB application which gives the same interface as that of the Base band Processor (BBP) at the MAC boundary. The proposed architecture replaces the physical medium by emulating the real PHY interface thereby eliminating the need for actual PHY during the MAC validation phase. By using this proposed architecture...
In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communication domain specific processor, and then proposes a novel processor architecture for the next generation wireless communication named GAEA using this design flow. GAEA is a shared memory multi-core SoC based on Software Controlled...
Full-fledged software radio platforms are complex and expensive systems, focused on signal processing, and not very suitable for easy development and large scale experimentation. We propose a Multi-Processor System-on-Chip (MPSoC) prototyping platform targeting the support for flexible radio. This platform is fully customizable at every layer of the wireless networking stack, making it easy to prototype...
This paper describes the implementation of a 64-point FFT on a Multi-Processor System-on-Chip (MPSoC) composed of 9 homogeneous clusters. Each cluster is built around a RISC processor. The implementation technique adopted for the mapping of the FFT produces a speed-up of 6?? which is close to the theoretical limit. This is due to a reduced overhead of intra-clusters communication.
We have designed a coarse-grained, dynamically reconfigurable architecture, specifically for implementing the wireless MAC layer in consumer hand-held devices. The dynamically reconfigurable MAC Processor is a SoC architecture that uses a reconfigurable hardware co-processor to delegate critical tasks. The co-processor can reconfigure packet-by-packet, handling upto 3 data streams of different protocols...
A WATM interface card using SOPC technology is presented in this paper. WATM is an extension of fixed ATM networks, and provides users wireless access to broadband services. The SOPC technology, developed by Altera Corporation, consists of a FPGA (field programmable gate array) and a Nios embedded processor. This paper introduces a novel method for design and implementation of WATM lower protocol...
The dynamically reconfigurable MAC processor is an innovative architecture specialized for the wireless MAC layer, and aimed at consumer hand-held devices. It is a software/hardware partitioned platform where the microprocessor uses a reconfigurable hardware co-processor to delegate critical tasks. This allows the microprocessor to handle fast and complex MAC protocols while clocking at relatively...
A connection bridge for connection of two CPU systems in SoC of the HAB (healthcare apparatus on body/bed) in home healthcare wireless network is addressed. Multi CPU system in a SoC could be divided into different part according with data process function. Therefore the each part of the system can work independently without influence each other. With the discussion of the performance of HAB and home...
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