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Evaluating the system in early design steps is critical for an efficient design of Multi-Processor SoCs (MPSoC). When the number of processors grows, the simulation time tends to increase exponentially. Native co-simulation has been proposed to obtain performance estimations with sufficient accuracy while requiring short simulation times. In MPSoC architectures buses often become the most important...
Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. With the increase in the design complexity of MPSoC architectures that must support these constraints, flexible and accurate simulators become a necessity for exploring the vast design space solutions. In this paper, we present an asymmetric...
With the increase in the design complexity of MP-SoC architectures, flexible and accurate processor simulators became a necessity for exploring the vast design space solutions. In this paper, we present a flexible cycle-accurate ISS model based on ArchC 2.0 language. The model can have a variable pipeline depth and can be integrated easily in any SoC design based on SystemC. Its performance and capabilities...
In 2010, a wave of consolidation swept over the Electronic System Level (ESL) design industry. It brought ESL providers together with mainstream EDA houses and created opportunities for new ESL ventures. This paper contains short summaries of presentations in a special session focusing on the future of ESL. The session has two goals: the first is to present the state of the art in ESL tools and practice...
This paper presents CODESL, a SystemC-based hardware-software co-design and co-simulation framework for embedded systems based on system-on-chip (SoC). This modelling platform, which works at Electronic System Level (ESL), enables early system functionality verification, as well as algorithm exploration before the final implementation prototype is available. It can validate the behaviour for both...
A system-on-chip hardware/software co-design platform was presented based on model driven-based design method. After the overall architecture of platform was described, four design levels and three mapping processes were introduced. Some key techniques were explained in detail, such as hardware/software partitioning algorithm based on genetic algorithm & constraint task scheduling, UML profile...
This paper presents a method for designing SystemC-compliant Instruction Set Simulators (ISS) that address three of the major problems system designers are faced with when modeling MP-SoCs architectures: the multiple levels of abstraction of the simulation models supporting the design space exploration, the simulation speed, and the debug of the multithreaded embedded application. First, this paper...
The quantitative exploration of the memory design space is needed early in the design process of deeply embedded systems. For predictive results, models are required that carefully consider three performance-impacting effects of memory accesses: synchronization, arbitration, and latency. Our approach combines functionally-correct performance simulation with memory models of different accuracy. Extending...
Telecommunication applications require an increasingly high throughput; their task graph often exhibits a high level of coarse grained parallelism. We extend the KPN model by multiple writers and readers and present the SystemC based co-design of a packet classification application on a multi processor system on chip.
The increasing complexity of embedded systems imposes system designers to use higher levels of abstraction than RTL in order to model, validate and analyze a system performances. It permits to prevent costly redesign efforts at RTL, which can adversely affect time-to-market. For this purpose transaction level modeling (TLM) approach is used. It allows the designers to rapidly verify and develop their...
Currently multiprocessor embedded systems are the principal vectors of semiconductor industry. Modelling, validating and analyzing a system performances impose the evolution of the traditional simulation techniques. In this paper we define the methodology we used in constructing the STARSoC co-simulation environment. This platform aims to explore at higher levels of abstractions a multiprocessors...
System architects working on SoC design have traditionally been hampered by the lack of a cohesive methodology for architecture evaluation and co-verification of hardware and software. This paper focuses on a comprehensive analysis framework providing platform assembly facilities, system analysis tools, enhanced traffic model and SystemC TLM IP. This framework has been intensively used to design and...
Mobile video processing as defined in standards like MPEG-4 and H.263 contains a number of timeconsuming computations that cannot be efficiently executed on current hardware architectures. The authors recently introduced a reconfigurable SoC platform that permits a low-power, high-throughput and flexible implementation of the motion estimation and DCT algorithms. The computations are done using domainspecific...
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