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High power consumption has significantly increased the cooling cost in high-performance computation stations and limited the operation time in portable systems powered by batteries. Traditional power reduction mechanisms have limited traction in the post-Dennard Scaling landscape. Emerging research on new computation devices and associated architectures has shown three trends with the potential to...
The Electrical interaction and the signaling process between a neuron and a metal oxide semiconductor field effect transistor (MOSFET) in a nanostructure circuit have led to a growing interest in computer brain interface. A wide variety of neuron silicon sensors and systems have been developed [2]. Typically, such brain chip interfaces rely on miniature sensors/electrodes that can get inside the interfaces...
This work presents a CMOS technique for designing and implementing a biologically inspired neuron which will accept multiple synaptic inputs. The circuit accepts synapses as inputs and generates a pulse width modulated output waveform of constant frequency depending on the level of activation. Next, the behavior of this implementation has been presented, and the realization of various basic logic...
In this work, design of low-voltage low-power analog artificial neural network (ANN) circuit blocks by using subthreshold floating-gate MOS (FGMOS) transistors and a neuron circuit is implemented. The circuit blocks, four-quadrant analog current multiplier and FGMOS based differential pair, have been designed and simulated in CADENCE environment with TSMC 0.35μm process parameters. Using the proposed...
Spiking neuron models, which simplify the biological neuron function, have attracted much attention recently in the fields of computational neuroscience and artificial neural networks. In these models, generation of post-synaptic potentials (PSPs) is an essential function. In this paper, we propose a new nanodevice structure using a nanodisk array connected to a MOSFET for spiking neuron models. The...
We present a circuit architecture for compact analog VLSI implementation of the Izhikevich neuron model, which efficiently describes a wide variety of neuron spiking and bursting dynamics using two state variables and four adjustable parameters. Log-domain circuit design utilizing MOS transistors in subthreshold results in high energy efficiency, with less than 1 pJ of energy consumed per spike. We...
This paper proposes new method for optimize and verified electric characterization graph of MOSFET by using artificial neural network. Optimization using neural network (ONN) will compare current-voltage (I-V) characteristic graph between the TCAD simulation and TSPICE modeling as desire data control a model parameter of BSIM. In this paper, the neural network method is dynamic feedforward neural...
A model of the neuroelectronic junction established by interfacing neurons to carbon nanotubes vertically grown on the surface of an open-gate MOSFET-based recording device was developed to simulate and analyze the induced extracellular neuronal electrical activity under temperature variations.
This paper presents modeling nanometer MOSFETs by a neural network approach. The principle of this approach is firstly introduced and its application in modeling DC and conductance characteristics of nano-MOSFET is demonstrated in details. It is shown that this approach does not need parameter extraction routine while its prediction of the transistor performance has a small relative error within 1%...
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