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Negative Bias Temperature Instability and Channel Hot Career degrades the life time of both the analog and digital circuits significantly and should be a major concern in nanoscale regime. These problems are usually addressed by leaving large design margins (called overdesign) or employing complicated calibration algorithm both of which result in larger area as well as excessive power consumption...
Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and significant parametric variations. Asynchronous circuits have the great potential to achieve delay insensitive, high performance and low power nanoelectronic design, while the existing asynchronous circuits do not guarantee logic and timing...
Nanoelectronic systems are extremely likely to demonstrate high defect and fault rates. As a result, defect and/or fault tolerance may be necessary at several levels throughout the system. Methods for improving defect tolerance, in order to prevent faults, at the component level for QCA have been studied. However, methods and results considering fault tolerance in QCA have received less attention...
It is widely recognized that device and interconnect fabrics at the nanoscale will be characterized by an increased susceptibility to transient faults. This appears to be intrinsic to nanoscale regimes and fundamentally limits the eventual benefits of the increased device density, i.e., the overheads associated with achieving fault-tolerance may counter the benefits of increased device density --...
Quantum dot cellular automata (QCA) is one of the emerging nanotechnologies for the design of next generation nanocomputing systems. However, excessive defects at the device level are expected to become a fundamental obstacle for achieving reliable computation in QCA-based integrated systems. In this paper, we present an information-theoretic approach to investigate the relationship between defect...
Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield in nano-technology, makes self repair communication channels a necessity in design of digital systems. This paper proposes a reliable NoC architecture based on specific application mapped onto an NoC. This architecture is capable of recovering...
A high level of redundancy is required to deal with the challenge of high defect and fault rates in nano environments. The reconfigurability of nano devices and the regular structure of nano fabrics make reconfiguration based repair an essential approach for both defect and fault tolerance. Ideally, repair based approaches have the best hardware efficiency when full sharing of redundancy is achievable...
Predicted device reliability for nanoelectronics indicates that redundant design will be necessary to build reliable nanosystems. Up to date, several fault tolerant techniques have been proposed and analyzed. However, the fabrication complexity of those circuits, which directly affects the final circuit reliability, is not usually considered. In this paper, we compare two fault tolerant techniques,...
To make digital circuits with unreliable devices more reliable has been a big challenge, especially for today's nanoelectronic circuit design. This paper presents a gate replication architecture towards increasing the reliability of individual nano-scale digital logic gates. We focus on deriving the fundamental relationship between gate replication and reliability improvement, and report both theoretical...
This paper investigates the behaviors of multi-island structure as an alternative redundancy scheme for single-electron tunneling (SET) based digital circuits. In particular, we focus on an SET logic gate (2-input NAND gate) to explore the role of this structure in improving the immunity against random background charges. Also discussed are the parameter selection with multi-island structure, and...
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