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Majority voted redundancy is increasingly implemented in fault-tolerant design today. In this technique, a voter receives parallel bits from an odd number of digital components and votes for the majority. Reliability improvement is the main focus of every fault tolerant system design. In this paper, we first present a viable alternative to the voting redundancy concept in order to significantly increase...
Negative Bias Temperature Instability and Channel Hot Career degrades the life time of both the analog and digital circuits significantly and should be a major concern in nanoscale regime. These problems are usually addressed by leaving large design margins (called overdesign) or employing complicated calibration algorithm both of which result in larger area as well as excessive power consumption...
In this paper, a methodology is presented to perform automatic selective TMR insertion on digital circuits, having as a constraint the required reliability level. Such reliability is guaranteed while reducing the area compared with TMR.
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
To make digital circuits with unreliable devices more reliable has been a big challenge, especially for today's nanoelectronic circuit design. This paper presents a gate replication architecture towards increasing the reliability of individual nano-scale digital logic gates. We focus on deriving the fundamental relationship between gate replication and reliability improvement, and report both theoretical...
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