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The trend to increase the number of cores integrated on a single die makes Networks-on-Chip (NoCs) a key component from the interconnection viewpoint. Unfortunately, continuous scaling of CMOS technology poses severe concerns regarding failure mechanisms, such as NBTI, that are crucial in achieving a reasonable component lifetime. Furthermore, the leakage power became more and more a critical issues...
Nano-electro-mechanical switches (NEMS) offer new possibilities for the design of ultra energy-efficient systems; however, thus far, all the fabricated NEMS devices require high supply voltages that limit their applicability for logic designs. Therefore, research is being conducted to lower the operating voltages by scaling down the physical dimensions of these devices. However, the impact of device...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
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