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Design of robust power supply system to support DDR4 interface operating at 2400Mbps and beyond requires full consideration of supply noise impact on timing jitter in the system. Using relative jitter for DQ vs DQS and CA vs CK is critical and absolute jitter for CK is critical in optimizing the power supply system and deriving supply noise mitigation strategy.
The continuous increase of demand for radios navigators makes the use of Automatic Test Equipments compulsory, in order to reduce the testing time and cost. The Telemakos is an Italian test equipment specifically designed to check radio navigator sensitivities. The paper reports the electromagnetic compatibility analysis carried out to meet the noise specifications. The Telemakos test bench is a very...
As DDR speed continues to increase, uncorrelated timing jitter becomes a significant portion of channel timing budget. The dominant component of uncorrelated timing jitter comes from power supply noise induced jitter (PSIJ). DDR systems rely on tracking of this jitter between data and strobe signals. Due to inherent 90 degree offset between data and strobe signals, a significant amount of high-frequency...
A link breaking methodology is introduced to reduce voltage degradation within mesh structured power distribution networks. The resulting power distribution network combines a single power distribution network to lower the network impedance, and multiple networks to reduce noise coupling among the circuits. Since the sensitivity to supply voltage variations within a power distribution network can...
This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes...
This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a gate delay at all the switching timing within a cycle, and devised an efficient sensitivity calculation of timing to decap for decap allocation. The proposed method, which is based on a statistical noise modeling and timing analysis,...
This paper describes several methodologies based on a pulsed laser beam to reveal the architecture of a high integrated SDRAM, and the different classes of Single Event Effects that can occur due to cosmic radiations. At cell level, laser is used to reveal an important technological parameter: the lithography process. At memory array level, laser is a powerful tool to retrieve cell physical arrangements,...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
Optical communication systems based on dense wavelength division multiplexing (DWDM) would benefit from the ability to adjust the operating wavelength of a laser transmitter. Previous attempts, including thermal adjustment, etalon based wavelength locking, and various types of optical frequency and phase locked loops such as the Pound-Drever-Hall technique suffer from weaknesses including sensitivity...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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