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Negative wetting is a common phenomenon in SMT wave solder process, especially happened when the size of the component is big, such as electrolyze capacitors. The cap of the electrolyze capacitors is like a heat sink and it lowers down the lead temperature of the top of the component during SMT wave solder process and that often causes negative wetting phenomenon on the PTH (Planting through hole)...
This study presents a method to predict lifetime of SMD lead free solder joints submitted to vibrations. An experimental method is presented to test chip resistors under vibrations. A specially designed testboard allows testing several specimens simultaneously. The time to failure is electrically detected. The experimental method is simulated using the Finite Element Method (FEM) in order to correlate...
In the 1960's surface mounted technology was developed. This technology as an alternative for through-hole technology made it easier to place components on both sides of the board by soldering, decreased package sizes, simplified assembly and reduced costs. Furthermore, higher mechanical robustness was obtained. In this paper, a numerical-experimental study is performed to investigate the robustness...
A novel stacked converter construction technology, Power Sandwich that lends itself towards automation and high power densities has been proposed. In Power Sandwich technology, new double-sided SMT x-dim components that have uniform height are stacked between planar substrates in a few stack layers. Double-sided x-dim components are soldered to both top and bottom sides. The concept of Power Sandwich...
As far as components with flip chip interconnects are concerned, one of the popular packaging solutions available in the market is thermally enhanced flip chip ball grid array (TEFCBGA) packages, which target mid to high performance applications. Traditional as it may be, the development of a reliable TEFCBGA package is still a very challenging task. The demands for high electrical performance with...
The board level drop test is intended to evaluate and compare the drop performance of surface mount electronic components. The JEDEC standardize for board level drop test address test board construction, design, material, component locations and test conditions etc. However, in actual drop test conditions, continued drops usually loosen up the mounting screw consequently. This situation may cause...
In this paper, a new application of 4-point cyclic bending test for the solder joint reliability evaluation is discussed. In light of the long cycle time of thermal cycle testing, the industry has been searching for a more cost-effective and time-effective way to achieve the evaluation task. The 4-point cyclic bending test is considered a good candidate in this study. The thermal cycle test and 4-point...
The board-level reliability of a 6-layer polyimide-based coreless flip chip package assembled on a printed circuit board (PCB) under a temperature cycling condition of -55 ~ 125??C was investigated in this study. The assembly of coreless flip chip package was achieved by a 17 mm ?? 17 mm die with 4355 Sn37Pb solder bumps, an amine-based underfill and 1521 Sn3.0Ag0.5Cu solder balls, no defect such...
Solder joint crack is a common failure mode of printed circuit board assembly (PCBA) for electronic products. In order to investigate the crack behavior of fine-pitch SMT solder joints, accelerated thermal cycling (ATC) up to 1500 cycles was performed on advanced PCBAs with low-profile thin small outline package (TSOP). The functional examination result shows that the failure rate of TSOP solder joint...
We examine an elongated bi-material adhesively bonded or soldered assembly with a continuous compliant attachment (bonding layer). The assembly is subjected to external tensile forces and bending moments applied to the ends of one of its components. We develop a simple and physically meaningful predictive analytical (ldquomathematicalrdquo) model for the evaluation of the interfacial shearing and...
The board level drop test is intended to evaluate and compare the drop performance of surface mount electronic components. The JEDEC standardize for board level drop test address test board construction, design, material, component locations and test conditions etc. However, in actual drop test conditions, continued drops usually loosen up the mounting screw, which is not considered in JEDEC. This...
Ball Grid Array BGA packages are a relatively new package type and have newly become the package style of choice. Much high density, high I/O count semiconductor devices are now only offered in this package style. Designers are naturally concerned about the robustness of BGA packages in a vibration environment when their experience base is with products using more traditional compliant gull or J leaded...
Four process parameters including, the pad length, the pad width, the stencil thickness and the stand-off, are chosen as four control factors, and by using an L25(56) orthogonal array, the no-fillet chip component solder joints shapes with 25 different process parameters combinations are established. And then all the shape prediction models of the 25 solder joints are built through the Surface Evolver...
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