The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
3D packaging is one of the main emerging markets especially for mobile application within the last view years. Mobile devices are exposed and hence need to be reliable under to vibration or mechanical shock conditions. Therefore, material properties covering strain rate dependency have to be at hand within reliability studies. Miniature bulk specimens were utilized to gain stress and strain data at...
The demand for flip chip devices is rising to meet increasingly strict requirements for smaller package size, multiple-die stacking and higher interconnection densities. There are, however, two major issues facing the flip chip process, which are reliability impact by the stresses induced in the solder joints during reflow and high cost for underfill process and materials. Current alternatives to...
Negative wetting is a common phenomenon in SMT wave solder process, especially happened when the size of the component is big, such as electrolyze capacitors. The cap of the electrolyze capacitors is like a heat sink and it lowers down the lead temperature of the top of the component during SMT wave solder process and that often causes negative wetting phenomenon on the PTH (Planting through hole)...
Board level reliability is more representative of the reliability of a package operating in the field and fatigue due to loading with cyclical stresses is a major concern in solder joint reliability. In this paper, the board level reliability of two types of BGA packages CTBGA 228 and CABGA 160 under accelerated temperature cycling stress had been studied; each package contains a daisy chained die...
Prevalence of portable devices such as netbook led to increased concerns on drop reliability of FBGA. In order to investigate drop reliability, board level drop test according to Jedec is done in assembly and SMT company, whereas system drop test such as netbook drop test is processed in final product company. In general, the lifetime of Jedec board level drop test and the lifetime of system drop...
Thermal fatigue of solder joints is critical to electronic package performance and life consideration. Failure caused by device warpage (WPG) problems is a major challenge with demands for miniaturization and system integration in a faster, better, and cheaper environment. This paper discusses a relationship between warpage and thermal fatigue life time and failure mechanism under thermal cycling...
In this paper, the state-of-the-art results of research and development in wafer-level packaging (WLP) is reviewed. The paper starts from the introduction of several fan-in wafer-level packaging technologies. The focus is given on the fan-in WLP reliability performance as related to the structural differences. New failure mechanisms that appear in build-up stack layers are discussed. Next, emerging...
A dynamic substructural method (DSM) is developed to simulate the board level drop test of a wafer level chip scale package (WL-CSP). Parametric study on package location at the test board, printed circuit board (PCB) thickness and WL-CSP package thickness is conducted in the board level drop test simulations. The peeling stress and first principle stress of the solder joints are checked and discussed...
The use of anisotropic conductive adhesives (ACA) in flip chip interconnection technology has become very popular because of their numerous advantages. The ACA process can be used in high-density applications and with various substrates as the bonding temperature is lower than that in the soldering process. In this paper, six test lots were assembled using two anisotropic conductive adhesive films...
In this paper we discuss the lifetime prediction for Pb-free soldered flip chip components under combined temperature cycling (TC) and vibration loading in terms of the failure mechanisms related to solder joint fatigue. We show the results of several experiments including failure analysis and comparison of lifetime models. For this purpose finite element analyses (FEA) of the thermal cycling and...
As far as components with flip chip interconnects are concerned, one of the popular packaging solutions available in the market is thermally enhanced flip chip ball grid array (TEFCBGA) packages, which target mid to high performance applications. Traditional as it may be, the development of a reliable TEFCBGA package is still a very challenging task. The demands for high electrical performance with...
The automotive requirements have quite many challenges regarding semiconductors reliability performance, and there was no escape for small outline discrete packages. Some epoxy die attached discrete devices could not pass MSL requirements due to die attach separation, even with leadframe surface treatment and all other solutions. The brainstorming results showed soft solder die attach would be the...
Understanding of interface fracture behavior of the solder joints has long been significant in reliability evaluation of electronic components and packages. The experimental and finite element methods were employed to characterize the fracture performance of "Cu wire/solder/Cu wire" sandwich structured butt microscale solder joints with different sizes (75 to 425 mum in thickness and 200...
Interconnect reliability of Micro BGA in enterprise and portable electronics were studied. Two Micro BGA with similar dimension but different alloy compositions were used in the life testing to observe crack propagation mechanism under thermal cycling stress. Standard metallurgical x-section, dye penetration and SEM were performed at time zero as well as after thermal cycling on 1st pass Micro BGA-solder-PCB...
CBGA (ceramic ball grid array) is one kind of advanced package for FPGA, which can fulfill the demands of high interconnect density, high thermal and electronic performance, high chip-assembling yields, high reliability. But in multiple loading environments, CBGA has the invalidation mode of solder joint thermal-mechanical failure, which will influence the long term reliability of FPGA circuits. But...
PbSnAg solder was widely used in die attachment for high power chip packaging, and the thermal-mechanical reliability of PbSnAg solder layer is a key factor to evaluate the quality of high power devices packaging. Viscoplastic finite-element simulation methodologies were utilized to predict Pb92.5Sn5Ag2.5 solder joint reliability for die attachment under accelerated temperature cycling conditions...
The thermal-mechanical reliability of solder joints has been a key issue in the reliability assessment of electronic packaging. The recent developments in constitutive model of solder joints are summarized. Numerous constitutive models are proposed such as elastoplastic model, creep model, separated viscoplastic model, uniformed viscoplastic model and constitutive model based on fracture mechanics...
Die size effects on chip package interaction for Cu/ultra low-k interconnect in flip chip package were investigated using mechanical and thermal analysis. The analytical and the theoretical study suggested that the die size effects were not caused only by the mismatch in CTE between die and substrate. By considering the number of bonding solder and its mechanical property during the cooling process,...
Continuous increase in demand for product miniaturization, high package density, high performance and integration of different functional chips has lead to the development of three dimensional packaging technologies. Face-to-face silicon (Si) dies stacking is one of the three dimensional (3D) packaging technologies to form a high density module. In this work, a chip level stacked module was demonstrated...
This paper presents a reliability model for wafer level chip scale packages (WLCSP) assembled with Sn4%Ag 0.5%Cu (SAC 405) solder. The reliability model is based on a creep constitutive model that takes into consideration the dimensions of the solder joints and a thermo-mechanical fatigue crack growth model. The creep constitutive model was derived from over 250 constant load creep tests performed...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.