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The single event transients (SETs) are a common source of malfunction in nano-scale CMOS integrated circuits. For this reason, evaluation of the SET effects and application of appropriate measures for their mitigation are fundamental tasks in the design of advanced radiation hardened integrated circuits. In general, SET analysis is based on the multi-scale modeling and simulation approach comprising...
Data retention and power consumption during the hold mode of operation of a SRAM cell is of high importance. Hence, there is a need for a cell design that improves Static Noise Margin (SNM) and consumes low static power. This paper presents a Schmitt-Trigger (ST) based Single-Ended 11T SRAM cell that uses dual-threshold CMOS technology which exhibits high read and hold SNM and consumes low power during...
The VLSI architecture for the low power combined FM0 and Manchester encoder (SOLS) circuit using modified GDI has been proposed in this paper. Comparisons are made with existing architecture using general CMOS Logic. The power consumption and delay in this circuit are reduced. The working conditions for existing circuit for FMO/Manchester encoder and decoder using HCPM technique have also been modified...
The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus minimising any hot carrier injection and dielectric stress degradation. The presented voltage extension technique is scalable to larger and smaller...
A masterslice (gate array) design can provide fast turn-around time on chip fabrication by sharing a pre-fabricated common array, but typically results in low circuit density and performance because of limited freedom of wiring the fixed transistor array. On the other hand, a masterimage (standard cell) design can achieve higher circuit density and performance by customizing circuit layout and placement,...
In the conventional array multiplier, the multiplication speed is restricted by the carry propagation. On the other hand, it is difficult to realize a compact multiplier in the high-speed multiplier such as the Wallace tree multiplier, because its layout is complicated and a large area is required for the interconnections. In such situations, the use of multiple-valued logic in conventional digital...
The performance limitations of the single cell FAMOS transistor have hindered the development of high speed MOS EPROM's that can match Bipolar PROMs for speed. Previous approaches to high speed MOS EPROMS have centered around a 4-T 11 I or a 2-T cell with It's inherent die area disadvantage and, hence, resulted in their manufacturable densities being limited to under 64K.
The conversion time for high-speed analog-to-digital converters is limited by the rate at which the internal comparator(s) can amplify small voltages 1 into logic levels. Several comparators have been designed with response times of less than 10 ns [1,2]. However, these circuits are usually fabricated with bipolar transistors.
Monolithic CMOS photonics seeks to minimize total transceiver cost by simplifying packaging, design and test. Here we examine 25 Gb/s applications in the context of integrated transistor performance and demonstrate a 4λ×25 Gb/s reference design.
This paper presents a 0.325-THz single-ended amplifier designed in a 28-nm FDSOI CMOS technology. The amplifier consists of four common-source gain stages and utilizes staggered-tuning along with inductive feedback (drain to gate) technique to boost up the gain over a wide frequency band. Having a total power consumption of 28 mW, the amplifier achieves a peak gain of 4.5 dB at 325 GHz. To the best...
A novel class-AB Flipped Voltage Follower is proposed, suitable for low-voltage low-power CMOS implementation in advanced technology nodes. Simulations have been performed using STMicroelectronics models for the 45nm technology. The Flipped Voltage Follower allows low output impedance and high linearity by means of a feedback loop. However, like the conventional common-drain voltage follower, it has...
III–V integration on Si is one of the most attractive options to extend future CMOS circuits. However, direct material integration by epitaxial growth is challenging mainly due to the large lattice mismatch. Here we present a novel technique that enables InAs and GaSb nanowires to be grown on Si substrates in the same MOVPE run. By reducing the Au seed size, the nucleation of GaSb can be suppressed...
In this paper a Reliability-AwaRE (RARE) method based on the gm/ID-methodology is presented which allows designers of integrated analog circuits to consider process as well as environmental variations and aging effects already at early design stages. The proposed method makes aging simulations on system level superfluous by utilizing a stochastic Look-Up table. The stochastic LUT contains simulated...
This paper presents a new second-order temperature-compensated current reference which uses only one resistor. The behavior of the proposed bias circuit is analyzed in this paper, and the current reference circuits were designed and simulated in a 130 nm CMOS technology. From the simulation results, the proposed current reference achieved 327 ppm/°C in the temperature range of −30 °C to +150 °C, which...
In comparison with conventional operational amplifier, ring amplifier can achieve better power efficiency for switched capacitor circuits. However, the cascade-inverter architecture of ring amplifier may suffer from undesirable oscillation which has a great impact on transient stability. This paper presents a latched-based ring amplifier which is capable of decreasing the probability of oscillation...
In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded...
The Internet of Things (IoT) became superior innovation area for nanoelectronic circuit design. This work is focused on a multi-modal power gating design approach for sensor node systems for IoT. Power gating is very efficient and flexible way for minimization of IoT CMOS circuits power consumption. However, only a very few papers suggesting multi-modal approach were published. Conventional power...
In this paper we show that the area optimization of STT-MRAM bitcells can deliver a substantial reduction in the energy per write access when dynamic voltage scaling (DVS) is adopted. Indeed, the increase in the bitcell area enables the reduction in the write energy consumed by the bitcells at the expense of the energy of peripheral circuits, when lowering the supply voltage. The proposed approach...
A wideband, CMOS current driver for bioimpedance measurement applications has been designed employing nonlinear feedback. With the introduction of phase compensation, the circuit is able to operate at frequencies higher than the pole frequency of the output transconductor with minimum phase delay. Moreover, it isolates the poles required for stability from the high frequency characteristics of the...
Filter-banks based on a gm-C topology are popular in acoustic sensor systems targeting spectral analysis. Their benefits lie in a very low power consumption and center-frequency scalability through gm-tuning to cover the audio frequency range. However the linear signal swing at the output of the filter is limited due to the inherent non-linearity of the input transistors in a differential pair. This...
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