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As the electronic packaging density continues to increase, flip chip or stacked packaging via bump bonding is gradually replacing traditional wire bonding and will become the mainstream packaging form in the future. For copper bumps, this new type of electronic interconnection has not yet been fixed by industry standards. Therefore, this paper has made a preliminary study on the reliability of this...
As the advancement of transistor nodes faces unprecedented challenges and work continues to extend Moore's law at the back end of the line (BEOL), packaging has become one of the fastest growing segments in the semiconductor industry. Lead-free soldering is one of the most critical steps in interconnection at the packaging level. The evolution of packaging requirements for various devices is driving...
In this paper, a novel 3D integration process named Via-Backside-Release process, abbreviated as VBR process, is proposed and technical issues are addressed. With VBR process, there's no need of removal process of copper overburden due to the filling of TSV by copper electroplating, and no individual unit process for producing Cu/Sn microbumps. In order to verify the feasibility of VBR process, a...
Low cost electrodeposited Sn3.5Ag solder bumps fabrication technology was developed for three-dimensional packaging applications. Effect of reflow time on interfacial reaction of electroplated Sn3.5Ag solder bumps with Cu under-bump metallization (UBM) was investigated. The microstructure of eutectic Sn3.5Ag is composed of β-Sn phase and Ag3Sn IMCs in the solder region. At the interface between solder...
In this paper, at first electroplating of copper and tin is optimized to fabricate micro-bump. Chip-to-chip bonding process is developed. Then, a temporary bonding process is developed and verified by experiment. And finally, a process for manufacturing multiple layer stacked chip module is designed and prototype of a 4 layer stacked chip module is fabricated successfully.
A number of new bonding techniques are emerging with the development of three dimensional (3D) stacking packaging. High temperature joint generated by low temperature process with traditional soldering process was one of the approaches to meet the bonding requirement for 3D packaging. Cu/Cu was bonded with joint gap of 100 micros and 60 micros via a layer of Sn plated on the Cu surface. Coupons were...
Cure Induced Micro-Anomaly (CIMA) are worm like hollow microstructures found within resin rich region of underfill after curing within a BGA package with combination of copper die bumps and Sn-Ag substrate bumps. CIMA leads to solder extrusion during secondary reflow. Root cause of CIMA has been identified to be from thermal mechanical stress induced by the stiffness of the joints formed between the...
A significant majority of component terminations are finished with electroplated tin. This finish offers a number of process advantages, but does have an intrinsic reliability issue. During ageing of the tin stresses can build in the finish that can result in the growth of a single crystal of tin out of the surface, a so-called tin whisker. Such whiskers can grow to a few hundred microns and cause...
We observed various EM-induced failures in current-stressed Cu/Sn/Cu flip-chip solder joints. EM-induced Cu-pad consumption occurred at the current-entry point (maximum current-density) on the cathode interface, and voiding occurred at the other joint corner away from the current-entry point (minimum current-density). We believe that the above various EM-induced failure modes were the result of different...
The mutual interaction between Sn/Ni and Sn/Cu interfacial reactions in a Ni/Sn/Cu sandwich solder joint structure has been discussed in this present work. The major interfacial reaction product on the Sn/Cu interface was Cu6Sn5 phase, while on the Sn/Ni interface, a ternary (Cu,Ni)6Sn5 compound layer was formed, instead of the typical Ni-Sn compound phase. On the other hand, an asymmetrical solder...
This paper reports a hermetic MEMS package structure with silicon wafer as bonded cap at wafer-level scale. CMP followed by spraying chemical smoothing process is utilized to thin the N(100) silicon cap wafer to the thickness of 150 mum after wafer-level Cu/Sn isothermal solidification bonding. Method for the thinning process and parameters for Cu/Sn isothermal solidification bonding process are researched...
A low temperature wafer-to-wafer bonding technology for 3D packaging/integration based on Cu-Sn isothermal solidification (IS) technology is introduced in this paper. The fluxless bonding technique using Cu-Sn multilayer composites to produce higher re-melting temperature bonding layer is presented. The structure of the intermediate multilayers and bonding patterns are designed, and the bonding process...
This work reports on the wetting behavior of electrolyte in fine pitch Cu/Sn bumping process by electroplating. Three methods containing adding complex wetting agent to electrolyte, plasma treatment to photo-resist and ultrasonic vibration were taken to improve the wettability between electrolyte and related materials. Contact angles of electrolyte containing different amount of complex wetting agent...
Interconnect reliability of Micro BGA in enterprise and portable electronics were studied. Two Micro BGA with similar dimension but different alloy compositions were used in the life testing to observe crack propagation mechanism under thermal cycling stress. Standard metallurgical x-section, dye penetration and SEM were performed at time zero as well as after thermal cycling on 1st pass Micro BGA-solder-PCB...
In this paper, we report a novel plating-friendly polishing mechanism for fabrication of high coplanarity and high density lead-free copper pillar bumps for advanced packaging applications. The final experimental results showed that the UIW (Uniformity in Wafer) could be sharply decreased from 6.37% after plating to 1.7% after polishing and even to 1.7% after reflow throughout the entire 4 inch wafer.
The chip to chip bonding technique using a Cu bump capped with thin Sn layers has been frequently applied to 3D chip stacking technology. We studied the effect of the microstructure on the joints. The joints were fabricated by joining micro-Cu bumps capped with Sn-Ag solder with sizes of 10 mum times 10 mum, 20 mumtimes 20 mum, and 30 mum times 30 mum to Cu pads capped with Sn-Ag solder at 245degC-330...
A model for the simulation of Kirkendall voiding in metallic materials is presented based on vacancy diffusion, elastic-plastic and rate-dependent deformation of the material. Starting with a phenomenological explanation of the Kirkendall effect we briefly discuss the consequences on the reliability of microelectronic components. Then, a constitutive model for void nucleation and growth is introduced,...
Because of their very high thermal conductivity, low melting point, and high shear compliance, indium-based materials are excellent candidates for thermal interface material (TIM) applications for packaging thermally sensitive next-generation devices. However, currently used indium-based solders suffer from 2 serious shortcomings: (i) high cost due to high indium content, and (ii) very low compressive...
This paper aims to provide a fine-pitch Sn/0.7Cu lead-fee solder bumps fabrication process that is characterized by using a novel plating-friendly polishing mechanism to transform the plated-based Sn/0.7Cu lead-free solder bumps with huge height deviation into smooth and uniform ones. The final experimental results showed that the UIW (uniformity in wafer) of Sn/0.7Cu solder bumps at 50 mum pitch...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
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