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This paper proposed a platform for rapid prototyping of high-speed and low-power embedded applications in networking. The concept utilizes the FPGA with the embedded processor to benefit from software flexibility and high performance of hardware processing. In comparison with the NetFPGA-cube, the proposed uG4-150 platform has significantly lower power consumption, cost and size.
In this paper, we perform the Electronic System Level (ESL) modelling and verification of two lossless compression standard algorithms for space applications using the SystemC language. In particular we present the architectures and a description in SystemC of the CCSDS-121 universal lossless compressor and the CCSDS-123 lossless compressor for hyperspectral and multispectral images. Both algorithms...
The Address Resolution Protocol (ARP) enables communication between IP-speaking nodes in a local network by reconstructing the hardware (MAC) address associated with the IP address of an interface. This is not needed in a Software-Defined Network (SDN), because each device can forward packets without the need to learn this association. We tackle the interoperability problem arising between standard...
For companies in the automation industry, the development of real-time Ethernet to connect devices is of high economic interest to replace conventional fieldbus systems. Therefore, many approaches for adapting Ethernet to real-time requirements come from industrial applications. This is a challenging task as the original Ethernet standard IEEE 802.3 was not designed for real-time data transmission...
A previously developed plug-in architecture for network-virtualization nodes allows network operators to introduce new types of virtual nodes and links and slice developers to use them in slices (i.e., virtual networks). In this paper, a method for extending network-virtualization infrastructures by introducing plug-ins to nodes in the infrastructure and a freely-designed plug-in-specific packet header,...
Although numerical range and precision are greatly improved for quadruple precision floating-point number in IEEE 754(2008) standard, the complexity of operation and cost of hardware resource for the quadruple precision floating-point has been significantly increased, especially for 113×113 mantissa arithmetic in floating-point multiplication operation. This paper presents a new quadruple precision...
Many cloud computing platforms adopt visualization technology to provide cloud services. To achieve high computing performance, many data parallel frameworks are adopted to run the jobs. The job is broken into pieces and farmed out to virtual machines (VMs) to process in parallel. The responses from these VMs are aggregated to produce the final result with concurrent flows. However, the concurrent...
This letter presents a novel framework for the design of adjustable reconfigurable partitions for the placement of variable-sized IP cores on embedded reconfigurable systems. It enables the rapid and easy to use methodology for the generation of adaptive computation and communication infrastructure for partial dynamic reconfiguration. The methodology allows an adaptable partition and efficient resource...
Network packet classification is a key functionality provided by modern routers enabling many new network applications such as quality of service, access control and differentiated services. Using ternary content addressable memories (TCAMs) to perform high-speed packet classification has become the de facto standard in industry. However, despite their high speed, one major drawback of TCAMs is their...
Hardware Trojan detection is a very important topic especially as parts of critical systems which are designed and/or manufactured by untrusted third parties. Most of the current research concentrates on detecting Trojans at the testing phase by comparing the suspected circuit to a golden (trusted) one. However, these attempts do not work in the case of third party IPs, which are black boxes with...
The main purpose of this paper is to refine the benefits of the FPGA-based synthetic instrumentation concept (see Section 1) proposed by us earlier [1] as well as to provide some new experimental data based on real industrial designs to show the efficiency of our methodology (see Section 2).
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