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An incremental delta-sigma modulator with a self-making capacitor having a high voltage operating ability for a 12-cell battery pack is proposed in this paper. The measured voltage range for each battery is from 0 to 5 V, and the maximum input voltage reaches to 60 V. The self-making capacitor adopting a metal over poly silicon with a relatively thin layer of oxide between the two plates is generated...
A new technique to reduce the clock jitter effect on single-bit continuous-time delta-sigma modulators (CTDSM) is proposed. It utilizes a delay line to generate N highly correlated clock sources to reconstruct the feedback waveform. Theoretical analysis show that the jitter-induced random noise power is reduced by a factor of 1/N2. Simulation results confirming the analysis are reported.
This paper proposes the use of FIR+SC DAC in sigma delta modulator is an approach to balance insensitivity to clock jitter noise and power efficiency. An example is implemented in UMC 180nm technology and simulation results show that it achieves SNDR 77.2dB and 83 μW power consumption in 100kHz bandwidth, which corresponds to FoMw 71fJ/conv.
This paper proposes a new compensation technique to reduce the clock jitter effects for the continuous-time sigma-delta (CT-ΣΔ) modulator by using divided-by-n (D-N) feedback DAC waveform. There are two types of clock jitter: independent clock jitter (random jitter) and accumulated clock jitter (deterministic jitter). This technique provides a useful approach to solve one of the critical non-idealities,...
We present a fully-digital digital-to-analog converter (FD DAC) architecture design for high-speed communication systems. The FD DAC design is based on the ΔΣ modulation. The specifications for the DAC includes a low 1.2 V supply voltage, a high 5 GS/s input sampling rate, and a wide 2.5 GHz bandwidth. We employ a combination of the time-interleaving, parallel, and pipelining techniques to reduce...
Rectifiers consisting of parallel connected 6-pulse bridges with modulation in DC current circuit show properties of multipulse rectifiers. A load unbalance of the component bridges of 12-pulse rectifier approximates the space vector to the case of rotating one. In consequence the shape of the line currents is close to sinusoidal one. In this paper the topology of multi-pulse rectifier with modulation...
A gain compensated op-amp for discrete-time ΣΔ modulators is described. The method greatly reduces the integrator's phase error caused by low DC gain on amplifiers. The scheme uses an additional unity gain buffer to correct the error caused by gains as low as 20 dB, thus enabling high-performance ΣΔ modulators in nanometer-scale CMOS technologies. Design strategies for op-amps and buffer designed...
This paper presents a differential SC second-order single-bit ΔΣ analog-to-digital converter (ADC). The converter has nominal conversion rate of 100 kS/s with OSR of 1000. Differential converter topology is used. This leads to lower second order harmonic and lower offset voltage compared to single ended topology. Together with SC implementation, the differential converter also makes it possible to...
Sine-shaping of feedback DAC current in continuous-time ΣΔ ADCs is an effective solution to enhance their immunity to clock jitter. In this paper, a simple mixer circuit for producing a sine-shaped output in continuous-time ΣΔ ADCs is introduced. The proposed solution does not need extra clock source or synchronization circuit, as the mixer utilizes the same clock applied to the comparator. It is...
This paper presents a sigma-delta modulator of two-order with switched-capacitors (SC) techniques for low power in 0.18 um CMOS process. Without continues current transmission SC techniques present a discrete low power system. And a low power op amplifier with discrete common-mode feedback and a dynamic comparator is also designed. This new amp works under the supply of 1.8 v and with the direct current...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
We designed and built a novel all-optical re-timing, re-amplifying, and re-shaping (3R) regeneration system based on terahertz optical asymmetric demultiplexers (TOADs) developed in our laboratory. The system is capable of parallel processing multiple wavelengths, a feature which will significantly improve the scalability of current wavelength division multiplexing (WDM) networks. Performance against...
This paper discusses the performance of the wavelet based filtered multi-tone (WFMT) modulation. The novel WFMT modulation was proposed in 2003 for improving characteristics of wireless and DSL multicarrier systems. In this paper we describe a main idea of WFMT and discuss the advantages of this novel modulation. The WFMT modulation in comparison with OFDM and DMT has low level of out-of-band side...
This paper studies efficient complex valued matrix manipulations for multi-user STBC-MIMO decoding. A novel method called Alamouti blockwise analytical matrix inversion (ABAMI) is proposed for the inversion of large complex matrices that are based on Alamouti sub-blocks. Another method using a variant of Givens rotation is proposed for fast QR decomposition of this kind of matrices. Our solutions...
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