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The short length and graded gap of InGaAs-based diodes with impact ionization are considered. Diode peculiarity is defined by usage region with varying composition. The analysis of diodes operation is performed by Monte Carlo technique. Influence of doping and composition profile on current-voltage characteristic of diode is investigated. The possibility of same direct motion of both types of charge...
In this paper, we introduce the Field Shielded Anode (FSA) concept that enables higher temperature operation of fast recovery diodes with planar junction termination. Conventional diodes utilizing local lifetime control principles show excellent dynamic properties at the expense of a higher leakage current, which is generated during reverse blocking when the space charge region penetrates into the...
In this paper we present a newly developed 1700V IGBT and diode chip set generation with optimized performances for 175°C junction temperature operations. The planar 1700V IGBT (SPT+) cell has been improved by exploiting the full potential of the N-enhancement layer with the consequent reduction of the conduction losses. In addition a substantial leakage current reduction has been achieved by designing...
The edge of the active area and termination structure have a decisive influence on the recovery safety operating area (SOA) of High Voltage (HV) freewheeling diodes (FWDs). We have investigated the HV planar anode diode that breaks the triangle trade-off limitations between the overall loss, the reverse recovery softness and the recovery SOA. Our results show the destruction phenomena during the recovery...
Design and characterization of a new generation of single-photon avalanche diodes (SPAD) array, manufactured by ST-Microelectronics in Catania, Italy, are presented. Device performances, investigated in several experimental conditions and here reported, demonstrate their suitability in many applications. SPADs are thin p-n junctions operating above the breakdown condition in Geiger mode at low voltage...
This paper investigates the physics of 0.13 mum partially depleted SOI gated diodes through TLP measurements and TCAD simulations. The impact of gate length, well type, oxide thickness, gate to contact distance and presence of gate on ESD performance are evaluated and discussed. It is shown that the gate coupling effect decreases ESD performance.
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