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This paper presents a high performance 1.2 V–0.18 μm CMOS voltage-to-frequency converter (VFC) that can be used either in single or differential mode. The proposed VFC works over the entire input range with output frequencies ranging between 0.1 and 1.0 MHz. Its operation is ratiometric, with low power consumption (80 μW), allowing its use in battery operated systems. It achieves high linearity (0...
In this paper a 8.2MHz-f@−3dB bandwidth Filter-&-Amplifier to be embedded in a DVB-T RX chain is presented. The filter has been integrated in 65nm CMOS node, working with a VDD/VTH ratio (supply/threshold voltage) as low as 2. Operating point issues due to low VDD/VTH ratio has been resolved by a proper bias circuit. Since such bias circuit is part of the filter circuit, its impact on filter performance...
This paper presents a micropower 1.2-V 0.18-µm CMOS temperature-compensated voltage-to-frequency converter for portable applications. Results show that the proposed converter has a power consumption of 60 µW (15 nW in sleep mode) operating over a (0.0 – 1.0 V) input voltage range with two different selectable output ranges, 0 – 0.5 MHz and 0.5 – 1 MHz. It achieves a relative error below 3 %, a gain...
A low-power and high-speed current-mode CMOS image sensor is proposed in this paper. Only one column-level transistor is used in the read-out circuit as a current conveyor to bias the in-pixel transistor operating in triode region. As a result, the current-mode read-out circuit is significantly simplified by the proposed structure, while saving the power by more than half. The proposed scheme enables...
This paper presents the analysis and design of a highly linear fully differential LNA based on the modification of active post distortion method. The analysis focuses on both nonlinearity and noise performance. The linearisation mechanism is investigated in terms of low frequency and high frequency theory based on Power and Volterra series respectively. A prototype LNA has been designed and is to...
This paper describes the design of a 3.1 to 4.8 GHz CMOS power amplifier (PA) for ultra-wideband (UWB) applications using TSMC 0.18-mum CMOS technology. The UWB PA proposed in this paper employs cascode topology with an additional common source stage to achieve high power gain. The current reused technique is implemented to enhance the gain at the upper end of the desired band for gain flatness and...
High data rates and increased digitization require A/D converters with high dynamic range and bandwidth. In combination with low power consumption they are key for broadband wireless systems. A single bit continuous-time DeltaSigma modulator with 10 MHz signal bandwidth avoiding high speed DEM circuits in 1.2V 90 nm digital CMOS is presented. It achieves an SNDR of 65 dB while consuming only 6.8 mW...
A graphical optimization method optimize the CMOS mixer is presented in this paper. The design constraints equations of gain conversion, noise figure, power consumption and IIP3 are presented in the same plane to find the optimal sizing of all components of CMOS mixer. The results show the sizing of components of up-conversion mixer and the optimal trade-off curve between high gain conversion and...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8 V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further,...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
This paper presents a novel design technique for low-distortion, micropower CMOS analog multipliers by adapting Gilbert's translinear principle to weak inversion. A non-linearity of 0.95% for input voltages of 0.5V and power consumption of 84??W have experimentally been obtained. The multiplier bandwidth is 30Khz for a bias current of 370??A.
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