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A voltage feedback charge-cancellation technique is proposed which prevents the conversion nonlinearity due to the parasitic effect of split DAC architecture in Successive Approximation Register (SAR) ADCs. A voltage feedback network operating as a capacitive charge-pump can efficiently detect and compensate the voltage error in each bit cycling, thus the conversion accuracy can be significantly improved...
A voltage feedback charge compensation technique is presented to prevent the conversion nonlinearity due to the parasitic effect of split capacitive DAC structure in successive approximation register (SAR) ADCs. The charge compensation is achieved by using an open loop amplifier that performs voltage feedback to the DAC array via a compensation capacitor, which is easy to be implemented with very...
A high-performance 13 bit current-steering DAC for analog subsystems is implemented in a standard 0.13 mum CMOS technology. A novel dynamic background calibration scheme directly trims the unary DAC-elements in differently weighted segments of the current source array. Interleaved current cells implement an effective RZ- behavior with NRZ output current waveform, which improves the dynamic linearity...
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