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The verification process in industrial context of embedded software in smart card is considered difficult, extremely time-consuming, and costly, with very few tools and techniques available to aid in the verification process. The work proposed in this paper consist to define the main architecture of testing java card application and a specific test model which consists of reducing a given java-card...
In this paper, we propose an efficient method for generating validation vectors for identifying delay marginalities under increasing levels of process-variations-across die, across wafers, across wafer lots. With the goal of significantly reducing the number of vectors required for validation, we propose an approach for segmenting the full global plus local process variation envelope into sub-envelopes,...
Services are highly reusable, flexible and loosely coupled, which makes the evolution and the maintenance of composite services more complex. Evolution of BPEL composite service covers changes of processes, bindings and interfaces. In this paper, an approach is proposed to select and generate test cases during the evolution of BPEL composite service. The approach identifies the changes by using control-flow...
In the work is formalized the problem of sustainable development of production, i.e. the optimum choice of parameter values of technological process with the purpose of minimization of the risk of obtaining the production of unplanned quality and of making incorrect decision about the quality of production and maximization of production profit at the guaranteed social and economic effects. Different...
Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
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