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Tip to Tip (T2T) of interconnect lines in advanced CMOS is quite important when downscaling the area of SRAM and logic standard cells. When T2T size is increasing we have less space for via placement. Additionally variability could impact the yield of the Dual Damascene (DD) structure because of via placement or alignment. As we continue to extend 193i lithography for patterning block using multi-patterning...
Self-aligned spacer double patterning (SADP) scheme has been proposed as an alternative to litho-etch-litho-etch (LELE) scheme because if its superior control of the lines that are patterned by a uniform and conformal deposition of a spacer layer along sidewalls of the sacrificial patterning lines. However, it adds process complexity in the film stacks and extra challenges on both the linewidth and...
We demonstrated the Si solar cell with ladder-shaped nanorod array, fabricated by combined the self-assembled lithography and reactive-ion etching technique. The measurement of angular reflective spectrums of the solar cell with ladder-shaped nanorod array using an integration sphere remained lower at broadband spectra and large angle of incident compared to the solar cell with micro-textured surface...
The challenges of deriving early-adopter competitive advantage, even with fabless access to process technology, through leveraging features offered by the advanced, and possibly disruptive, process technologies in real SoC products, are outlined. A structured methodology for addressing these challenges, and bridging the gap between process and design, sufficiently early in the development cycle to...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
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