The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Through Silicon Via (TSV) can be used to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency [1–3]. Via Reveal-a kind of wafer back side process moduleplays an important role in the successful implementation of TSV. In via-first and via-mid TSV integration flows, Si must be removed from the backside of the wafer to make contact with...
This paper reports a nanocone-forest silicon surface fabricated by an improved DRIE process using SF6/C4F8 in cyclic etching-passivation process, which is maskless, controllable, effective and large-size. As well known, optical property of textured silicon surface is determined mainly by its surface structure, and surface structure is determined by process conditions. In this work, process conditions...
The wafer thickness sensor (WTS) is an optical, non-destructive sensor that directly measures the etch depth of vias, without regard to aspect ratio. The high throughput measurements of via depth after the etching of through silicon vias (TSV) will allow timely feedback for process control, process development, and the prevention of process excursions in 3D IC process technology. In this paper, we...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
A dry process is developed for the etch-back of spherical silicon surfaces, intended for thinning of the emitter in spherical pn photodiode. The process is based on reactive ion etching, and enjoys higher reliability and controllability compared to wet etching. The process conditions are controlled to obtain an angle-dependent selective etch rate across the spherical surface.
A detailed study of the punchthrough formation mechanism induced by the walled emitter configuration is proposed. Efficient process and device simulation tools -IMPACT- have been used and results have been successfully compared to measured characteristics.
Low pressure plasmas of halogens, halo carbons and their mixtures are in general use for etching micron size features on Si, GaAs and InP. Several processing parameters may be varied to attain the optimum conditions for a particular process in terms of etching rates and profile control. The effects of the manipulation of process variables such as pressure, applied frequency, and gas feed composition,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.