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Nano-grain reconfigurable cells have the potential to replace memory-consuming LUT (Look-Up Table). However, the cells offering the highest area improvement are also those offering the lowest flexibility, i.e. not all the Boolean functions are available. Reaching the same flexibility of LUT is mandatory to reuse existing FPGA tool flows, which can be obtained by clustering cells in a matrix-like architecture...
An original and modern integrated current sensor is designed and presented in this paper. It can provide a sense current proportional to an output current available to the microcontroller via an external resistor. The ratio between output and sense current is modeled and simulated. The errors between the two currents increase in low currents domain. A solution consisting in a gate back regulation...
In this paper, we present a simple differential CMOS ISFET based pH sensor. The design uses two different sensing areas. The resulting sensor reduces complexity and power consumption making it suitable for implantable biomedical applications. The design is implemented in a standard 130nm process and the design constraints on sensitivity are explored. Analytical results based on theory show that sensor...
The fully differential class-AB OTA topology by Peluso presents a poor Common-Mode Rejection Ratio (CMRR) and could become unusable for a common-mode gain larger than 1. We propose a local feedback loop that exploits internal nodes and triode-biased transistors to improve the CMRR with a limited power and area penalty. Simulations in 40-nm CMOS technology show a net improvement of the CMRR without...
Regarding optimized logic network generation, recent papers have demonstrated that non-series-parallel topologies can deliver arrangements with fewer transistors when compared to the widely used series-parallel approach. However, due to its topology particularities, this paradigm represents a challenge for physical cell design, especially concerning the transistor placement procedure. In this scenario,...
An improved readout circuit interface for ion-sensitive field-effect transistor (ISFET) is proposed in this work. When compared with conventional topologies found on the literature, the proposed ISFET readout circuit presents at least two advantages. The first concerns the simplicity of the new circuity topology, and the second is the additional gain conferred to the sensor output signal. The performance...
In this paper, we propose efficient scalable nonvolatile flip-flops (NV-FF) with single-stage pulsed latch which is explored as the flip-flop core in hybrid CMOS/MTJ (magnetic tunnel junction) integration. Typical full-custom FF cores are implemented with a 28nm ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. The performance analysis takes into account...
The addition is the most used arithmetic operation in Digital Signal Processing (DSP) algorithms, such as filters, transforms and predictions. These algorithms are increasingly present in audio and video processing of battery-powered mobile devices having, therefore, energy constraints. In the context of addition operation, the efficient 4-2 adder compressor is capable to performs four additions simultaneously...
Layout design principles of IP blocks in the IC, and frequency mixers in particular, are discussed. Several variants of the layout design are carried out. They are modeled and compared to a schematic implementation. Qualitative assessment of implementations is carried out. The conclusions and the ways of improvement are proposed. The nature and the origin of deviations and variations in the process...
An automatic, defect-oriented method is proposed for activating latent defects in analog and mixed-signal integrated circuits. Based on the topology modification technique, added stress transistors generate voltage stress that activates these latent defects. This contrasts with burn-in testing which uses increased temperatures as a fault activation mechanism. Moreover, this Design-for-Testability...
The comparison element for a content-addressable memory is made on the STG DICE cell with transistors separated onto two groups and a logical element “Exclusive OR”. The comparison element contains two identical blocks that are spaced on the crystal by the distance of four micrometers. The simulation of the new 65-nm CMOS comparison element showed the resistance to impacts of single nuclear particles...
A wideband 2–3 GHz three-stage low noise amplifier (LNA) featuring current reuse, cascaded L-match input network, and multiple gated transistors method (MGTR) is designed in 0.18-μm CMOS technology. The current-reused topology is adopted to fulfill low power consumption, meanwhile, high gain and low noise are obtained. The cascaded L-match input network is used to enhance the input matching bandwidth...
Last few decades have shown that the low-voltage (LV) low-power (LP) IC designs have been given a great attention as power consumption has become a great challenge. This paper demonstrates implementation of OTA and its application in low pass filter design using bulk-driven MOS transistors (MOST), bulk-driven dynamic threshold MOST, bulk-driven floating-gate MOST and bulk-driven quasi-floating-gate...
Recent works demonstrate constant optimizations in the number of transistors necessary to implement some logic functions by using non-series-parallel arrangements. However, these kind of networks can produce non-dual and non-planar structures, which cannot be fully treated by some of the classical algorithms dedicated to placement. In this paper we present two methodologies to place and route non-series-parallel...
Despite their substantial power savings, voltage scaling design increases the concern about sensitivity to manufacturing process and operating conditions variations. These can induce significant delay changes in fabricated circuits. An elegant approach to cope with these issues is to employ quasi delay-insensitive asynchronous design styles, which allow relaxing timing assumptions, enabling simpler...
With the shrinking technology, new systems are designed that are miniature in size and perform faster operations. Adder is a basic circuit used for the purpose of addition. In a cascade design, the output of one circuit acts as an input for the other, so delay in the propagation of the carry generated while addition is major issue in the design of adders. When the circuit is designed with any other...
In this paper continuous time high-performance current mirrors (CMs) based on series and parallel connected unity sized CMOS transistors suitable for low power applications are presented. It is shown that the proposed implementation techniques allow an increased output resistance, from twice the output resistance of the simple current mirror (SCM) up to more than 50 times of the cascode current mirror's...
There exists a fundamental limit in improving the phase noise performance of LC-tank oscillators. Impediments to reach this limit are first discussed, and then a clipping LC VCO topology based on dual tank is presented to mitigate them. This topology can approach within 3 dB of the maximum thermodynamically achievable figure-of-merit (FoM) limit. Compared to conventional class-B/C/D/F oscillators,...
In the research of low power VLSI circuits, the use and implementation of Transmission Gate Based MUX-Latches for serial link interfaces has gained more attention at the gate level design. Multiplexer-latches (MUX-Latches) possess the logic function of combinational circuits and storing capacity of sequential circuits. By using pipeline topology with Transmission Gate MUX-Latch, many latch gates for...
This In this paper, we present a new inverter topology in order to decrease the process variability influence on performances of a ring oscillator. Using FDSOI technology, we used the back-gate electrode of the transistor to symmetrize the output of a complementary inverter. This technique will reduce the variability of the inverter and the jitter (i.e. the phase noise) of the ring oscillator. Complementary...
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