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Nano-grain reconfigurable cells have the potential to replace memory-consuming LUT (Look-Up Table). However, the cells offering the highest area improvement are also those offering the lowest flexibility, i.e. not all the Boolean functions are available. Reaching the same flexibility of LUT is mandatory to reuse existing FPGA tool flows, which can be obtained by clustering cells in a matrix-like architecture...
This paper presents the Field Programmable Gate Array (FPGA) based real-time implementation of Switching Angle (SA) method for the 81-level Trinary Cascaded Hybrid Multi-Level Inverter (TCHMLI) in the Xilinx Spartan 3A DSP FPGA using VHSIC Hardware Description Language (VHDL). The SA method is a non-carrier based switching modulation scheme. The simulation results of the MLI using Half Height Method...
This paper deals with the design and development of conventional Level-shifted PWM techniques in a field programmable gate array (FPGA) for asymmetrical converters in a Trinary Hybrid Multilevel Inverter topology. Each modulation technique has been implemented in FPGA through a 32-bit single precision floating point architecture in accordance to IEEE-754 standard. Portability to other devices is ensured...
A high power Y : Y/Δ three-phase Dual Active Bridge (DAB) topology offers higher power density, smaller switching stress, smaller volume of magnetics and smaller DC capacitor over single phase DAB. Therefore this topology is suitable for medium voltage (MV) applications. The high-frequency DAB currents are nearly sinusoidal suited for D-Q transformation which enables fast average mode current control...
This paper describes a novel design of a high voltage, high frequency, bipolar pulse generator, for experimental use in electrochemotherapy and irreversible electroporation, using RF MOSFETs (DE375-102N12A) in a cascaded multilevel inverter topology. Its pulsing regime is fully programmable and is con-trolled by an FPGA. A systematic development approach was followed. The UCC37321 gate driver and...
This paper proposes a fifteen level H-Bridge cascaded multilevel inverter with fundamental frequency switching for low power applications such as solar powered power supplies, battery powered standby power supplies. The effect of the variation of gate pulse on the performance of the inverter for different conditions of gate pulse variation is studied and simulation results are presented. Experimental...
The use of dynamically and partially reconfigurable resources permits to support complex applications. If dynamic and partial reconfiguration offers new possibilities for applicative implementations, it could also provide new ways to design efficient interconnection architectures. In this way, R2NoC, a Network on Chip constituted of dynamically reconfigurable routers is presented. First characterizations...
Emerging devices open the way to build nanoscale logic cells, dedicated to high-density reconfigurable computation. Nevertheless, in an architectural context, fine-grain logic cells integration is limited by traditional interconnection scheme and associated overload. This paper describes an interconnection scheme, based on static and incomplete interconnection topologies. We also propose a method...
Due to rapidly growing system-on-chip industry, not only the faster units but also smaller area and less power has become a major design constraint for VLSI community. Further, demand for high speed is continuously increasing. In processors, most commonly used arithmetic operation is the addition operation. It is the adder delay that determines the maximum frequency of operation of the chip. Different...
This paper presents the architecture and implementation of a configurable router intended for embedded network-on-chip support within field-programmable gate arrays. The router supports five network topologies and utilizes a dual-crossbar arrangement to reduce resource utilization. The router has been implemented in an Altera Stratix chip and in a 0.18-mum standard-cell process. For the routing and...
The way of on-board digital signal processing based on FPGA is studied. It contains requirement analysis of the on-board processing functional specifications, an on-board real-time digital signal processing system is designed with radiation tolerant FPGA. The design takes full advantage of the massively parallel architecture of the FPGA logic slices to achieve real-time processing at a high data rate,...
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