The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper suggests an improved method to round off the concave corners of the deep trenches formed by plasma etch. The corner rounding technique, sacrificial oxidation (SACOX) before gate oxidation, has been practiced on the shallow trench isolation (STI) to improve the CMOS leakage performance. However, the direct implementation of the SACOX on the deep trenched MOSFET having less than 0.5 um trench...
In this paper, we demonstrate that by introducing a high tensile Inter Layer Dielectric (ILD) in the fabrication process, the hook shaped saturation drain current (Idsat) behavior of NMOS can be reduced and totally eliminated in PMOS for 0.13um technology node. The hook shaped Idsat behavior is caused by the combination of mechanical stress due to Shallow Trench Isolation (STI) in channel width direction...
In this paper, a novel compact structure design for minimizing the chip area cost is proposed. The improvement in sensitivity and temperature drift for silicon piezoresistive force sensor is evaluated. The sensitivity improvement can be obtained by adding a long flexible cantilever, and locating stress-sensitive element at a high stressed area close to the bottom surface of the lower cantilever. An...
The impact of STI stress with layout dependency on circuit performance is investigated. A 3D stress simulator has been developed using finite element method, which considers both the layout design and process information (PDK). The mobility change due to stress is included in the transistor modeling for circuit simulation. The circuit performance can thus be analyzed with nonlocal stress. As a test...
We present the systematic study on dominant factors of the performance of scaled (110) n/pFETs. STI stress effects and velocity saturation phenomena in narrow and short (110) devices are investigated for the first time. Idsat of scaled (110) nFETs approaches (100) nFETs as a result of mu increase due to transverse compressive stress from STI in (110) nFETs and strong velocity saturation in (100) nFETs...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.