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Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6~1 nm EOT and low Vt of ~0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET...
An approach to nanoscale DG FinFET design for LP and HP nanoscale-CMOS applications via S/D engineering [i.e., control of NSD(y)] was proposed, and demonstrated to be viable by device simulations and measurements. The approach exploits the idea of allowing S/D dopants properly distributed in the channel for HP-Vt design. We demonstrated the design approach at the 45nm node. Scaling Lg to Lt10nm, as...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
In this paper, the authors have demonstrated high-performance inversion-type E-mode In0.65Ga0.35As MOSFETs using ALD high-k gate dielectrics such as ALD Al2O3 and HfO2 with a maximum inversion current as high as 1.05 A/mm and a peak transconductance of 0.37 S/mm. These results suggest In-rich InGaAs could be an ideal channel material which is easy to integrate with high-k dielectrics and has a higher...
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