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One and two dimensional nanocarbon (NC) materials, including carbon nanotubes (CNTs), graphene and graphene nanoribbons (GNRs) have excellent properties and can therefore be building blocks of future electronic devices. It has been predicted and demonstrated that transistor channels and interconnects (More Moore devices) made of NC materials have excellent properties [1-6]. NC-based Beyond CMOS and...
Silicon-on-insulator (SOI) SRAMs supported by a thin buried-oxide (BOX) film have been exposed to wide-range high-energy heavy ions for simulating terrestrial and galactic radiation impacts. Experimental results have demonstrated that a back-bias approach leads to a 100-times increase in their soft-error sensitivity compared to the counterpart zero-bias situation. This is attributed to that back biasing...
This work addresses on the fabrication of ion-sensitive field-effect transistors with the multiple Ω-shape nano-channels. The Ω-shaped channels with the width/space about 1∶1, 200/200 nm, were fabricated by the thermal nanoimprint lithography and the anisotropic/isotropic dry etching processes. The sensing properties of proposed ISFETs were studied and compared with the conventional single channel...
In this paper, the TCAD simulation of charge plasma based double gate junction-less transistor with channel length of 18nm is analyzed. The structure shows better ION/OFF ratio(107) compared to the conventional junction less transistors (JLT). The use of charge plasma concept for inducing n+-n+-n+ regions and generating free charge carrier for conduction makes the process of fabrication easier for...
We summarize several lines of investigation of foundry-processed patch-antenna-coupled Si MOSFETs as plasmonic detectors of THz radiation. First, we explore detection at frequencies as high as 4.3 THz, about one hundred times higher than the transit-time-limited cut-off frequency of the devices, searching for the fundamental limits of the detection principle. Then, we address the much-debated issue...
A substrate network tailored for a variety of transistor geometry including channel sizes, fingering and folding, and shapes and placements of guard bands, extends the capability and accuracy of full-chip noise coupling analysis of mixed technology VLSI integration. Analysis of substrate sensitivity of differential amplifiers in a 90 nm CMOS technology with more than 64 different geometry and operating...
This paper demonstrates the sensitivity analysis of a piezotransistor-embedded microcantilever sensor facilitated as platform for stress sensing applications. To enhance sensitivity and detection capability, different channel width-to-length aspect ratio transistors are designed and characterized under the mechanical strain at different gate bias. Higher sensitivity is found for the devices with lower...
In this paper, we report the presence of B10 based on SIMS analysis in SRAM arrays in the 90nm to 45nm technology nodes. The physical presence of B10 correlated very well with the thermal neutron soft error rate (SER) sensitivity of SRAM cells. This result confirmed that without BPSG layer in advanced Si technologies, there is still a high possibility of B10 contamination from the Fab process. Furthermore,...
Nano Beam Diffraction has been used to analyze the local strain distribution in MOS transistors. The influence of wafer process on the channel strain has been systematically analyzed in this paper. The source/drain implantation can cause a little strain loss but the silicidation step is the key process in which dramatic strain loss has been found.
This paper presents a comparator that is designed in an organic electronics technology on a flexible plastic substrate with p-type organic thin-film transistors (p-OTFT) only. The comparator has a gain of 12 dB and works at a supply voltage of 20 V consuming 9 muA. At a clock frequency of 1 kHz the input sensitivity is 200 mV. The comparator is designed following a threshold-voltage VT insensitive...
This paper describes several methodologies based on a pulsed laser beam to reveal the architecture of a high integrated SDRAM, and the different classes of Single Event Effects that can occur due to cosmic radiations. At cell level, laser is used to reveal an important technological parameter: the lithography process. At memory array level, laser is a powerful tool to retrieve cell physical arrangements,...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
This paper reviews recent experimental confirmations that the intrinsic radiation robustness of commercial CMOS technologies naturally improves with the down-scaling. When additionally using innovative design techniques, it becomes now possible to assure that performance and radiation-hardness are both met. An illustration is given with an original nano-power and radiation-hardened 8 Mb SRAM designed...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM=185 mV at 0.6 V), enabling sub-32 nm low-voltage design.
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
A 53 dB gain limiting amplifier for OC-192 and 10 GbE applications is developed in a 50 GHz fT SiGe SOI complimentary bipolar process, and has 5 mV pk-pk sensitivity, 1.25 V pk-pk maximum input signal, 14 ps (20/80%) rise/fall times and 450 mV pk-pk output into matched differential 50 Ohm loads, consuming 430 mW on a 3.3 V supply. Input Cherry-Hooper gain stages limit the -3 dB bandwidth to 11 GHz...
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