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We present a new method and its implementation that enables design-phase assessment of statistical performance metrics of semiconductor memories under random local and global process variations. Engineers use the tool to reduce design margins and to maximize parametric yield. Results on industry grade 45nm SRAM designs show that this holistic approach is significantly more accurate than the alternatives...
This paper presents an automated technique to perform SRAM wide statistical analysis in presence of process variability. The technique is implemented in a prototype tool and is demonstrated on several 45 and 32nm industry-grade SRAM vehicles. Selected case studies show how this approach successfully captures non-trivial statistical interactions between the cells and the periphery, which remain uncovered...
As CMOS technology scales, to consider process variation becomes increasingly challenging. Statistical gate delay model is widely used technique to analyze the influence of process variation on gate delay. We propose a second-order gate delay model which is more accurate even with the larger variance of variations. The number of additional variables introduced by second-order terms is minimized using...
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
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