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A new partially-thickened local (PTL)-interconnect structure with an extremely low resistance is developed for the 40 nm-node low-power CMOS device to boost the RF performance. The PTL-interconnect is featured by the Cu dual-damascene (DD) interconnect combined with the slit-contact (SLICT) in the low-k pre-metal-dielectrics (PMD, k=3.1), accomplishing 50% reduction in the resistance of metal-1 (M1),...
The mechanism of two kinds of via etch striation (type I and type II) has been investigated to improve contact resistance (Rc) uniformity and solve breakdown voltage (VBD) issue in 65 nm Cu low-k interconnects. Heavy etching polymer deposition on the sidewall of capping layer and rapid photo-resist (PR) consumption on PR shoulder are two main resources to result in via etch striation. The effects...
Bumpless interconnect of 6-mum-pitch Cu electrodes was realized at room temperature with the surface activated bonding (SAB) method. In this study, we propose a novel bumpless structure, where the electrodes and a surrounding Cu frame are fabricated with the same height to increase bond strength and demonstrate the feasibility of a sealing interconnection between Cu surfaces. The damascene process,...
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