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The increasing process variations which goes along with the continuing CMOS technology shrinking necessitate accurate statistical timing analysis. Multiple Input Simultaneous Switching (MISS) is simplified to Single Input Switching (SIS) in most of the recent approaches, which introduces significant errors in Statistical Static Timing Analysis (SSTA). Hence, we propose a new modeling and statistical...
The Wave Dynamic Differential Logic (WDDL) is considered as a relevant hardware countermeasure to increase the robustness of cryptographic devices against Differential Power Attacks (DPA). However, to guarantee its effectiveness, the routing in both the direct and complementary paths must be balanced, to obtain equal propagation delays and power consumption on differential signals.
Switching between line of sight (LOS) links and satellite links in an airborne network (AN) environment causes many challenging problems for the transport protocol. The typical bandwidth of a satellite link may be in the order of 1 Mbps and the round trip time (RTT) may be around 500 ms. The bandwidth of a LOS link is in the order of 300 Kbps and the RTT is just a few milliseconds. Therefore, switching...
In this work, we propose a clock scheduling algorithm that is used to mitigate the effects of clock skew that can arise from thermal run-time variations. Depending on the amount of skew, the algorithm selects a different minimum delay tolerance value in order to correct the skew problems, without the performance penalties that are associated with static worst-case scheduling policies. The design was...
With the advent of networks-on-chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distribution. Recently proposed schemes agree on a source synchronous design style with some form of ping-pong buffering to counter timing and metastability concerns. However, the integration issues of such synchronizers in a NoC...
As a basic block of a multi-switching-and-processing system, fast and fair arbiters are critical to the efficiency of multi-core computing units, high-speed crossbar switches and routers, which are the key to the performance of on-chip networking/computing in a SoC and NoC. In this paper, a High-Speed and decentralized round-robin arbiter (HDRA) is presented. Unlike the conventional round-robin arbiters,...
This paper analyzes the impact of simultaneous switching noise (SSN) on the timing behavior of CMOS digital blocks. The concept of instantaneous transfer function is introduced to interpret noisy signals and perform timing measurements on such signals. It is shown that the average swing during switching is the key parameter to predict the noise impact on the delay of a logic path, whereas the peak...
Logic cell modeling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behavior of CMOS cells with respect to the voltage signal at their input and output pins. A current-based model for CMOS logic cells is presented which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits. Existing current source models are...
Standard cell libraries are used extensively in CMOS digital circuit designs. In the past ten years, standard cell library size has increased by more than 10X. Reducing the library size is becoming a must. In this paper, we present an efficient piece-wise nonlinear library modeling format and library size reduction technique. Instead of using tables and vectors, this format uses base templates (curve...
As CMOS technology feature sizes decrease, random within-die and inter-die process variations more and more jeopardize SoC parametric and functional yield. Largely neglected in the state-of-the-art, dynamic energy consumption and power dissipation becomes heavily affected. This paper describes a technique to systematically bring statistically correlated timing/energy variations all the way up from...
Commercial crosstalk analysis tools are widely used for timing verification of LSI, but they analyze the worst case of crosstalk effect in any theoretical cases, which is really pessimistic. Some works have been done to reduce the pessimism based on deterministic method like logical correlation or timing window correlation. In this paper, a novel and practical crosstalk analysis introducing probability...
Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. Its implementation in a VLSI-CAD flow has been considered through the synthesis stage. In this paper we study the implications of place and route on voltage interpolation. We evaluate multiple placement strategies, and conclude...
This paper presents a variable timing controlled soft-switching inverter. The proposed timing control is based on a simple voltage sensing circuit that detects zero voltage crossing condition to determine the main switch turn-on time. The proposed technique can be applied to different types of zero-voltage switching type inverters. In this paper, the coupled-magnetic type soft-switching inverter is...
IR-drop problem during test mode exacerbates delay defects and results in false failures. In this paper, we take the X-filling approach to reduce IR-drop effect during at-speed test. The main difference between our approach and the previous X-filling methods lies in two aspects. The first one is that we take the spatial information into consideration in our approach. The second one is how X-filling...
Current discrete event simulator requires heavy simulation overhead to switch between different components to simulate them in strictly chronological order. Therefore, timed simulation is significantly slower than un-timed simulation. By simply adding delays in the components and communication channels, our timed MPEG-2 decoder simulates more than 14 times slower than an un-timed simulation. In this...
This paper studies the scheduling and assignment problem that minimizes the total energy including both dynamic and leakage energy for applications with loops on multi-voltage, multi-processor DSP. An algorithm, LSAMP (Loop Scheduling and Assignment to Minimize Power), is proposed. The algorithm attempts to minimize the total energy while satisfying timing constraint with guaranteed probability. We...
We show that rising and falling delays in gates can differ considerably. Simulation data, using 40 nm and 65 nm process technology, shows an increasing trend and that the slow transition delay could be two times of the faster transition delay. This translates to an asymmetry between the rise and fall delays along a path. Based on this we propose refinements to the following delay test methodology:...
In this paper, we consider the problem of selecting a set of aggressor nets that maximize crosstalk induced noise or delay pushout on a coupled victim net, under given logical constraints. We formulate the problem mathematically, and propose efficient Lagrangian Relaxation and network flow based approaches that guarantee an optimal solution. We also formulate and solve this problem while considering...
We present a new structural delay test methodology that identifies small timing anomalies in dual/multi core processor circuits by comparing the relative switching time of identical circuit paths in the multiple cores. A difference in switching delay beyond the statistically observed worst case within-die timing variation indicates a defect. The proposed test is purely a comparison test between identical...
As deep sub-micron (DSM) technology improves, the need for interfacing modules in multiple clock domains (MCD) is increasing. This work proposes a novel interfacing method for point-to-point communication between modules whose frequencies are rationally related. The introduction of two stages of FIFO-like interfacing registers makes this method skew tolerant. It also allows a slower module to receive...
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