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In the traditional Publish/Subscribe (Pub/Sub) paradigm, most of the responsibilities lie with the broker, thus making it burdened. It also takes a considerable amount of time to first route the publications and subscriptions towards the broker, and then to further route the notifications to the subscribers. This leads to delays in data delivery. Besides delay and bandwidth consumption, the number...
We analyze a classification of two main families of controllers that are of interest when the feedback loop is subject to switching propagation delays due to routing via a wireless multi-hop communication network. We show that we can cast this problem as a subclass of classical switching systems, which is a non-trivial generalization of classical LTI systems with time-varying delays. We consider both...
To alleviate the growing concern of energy waste in networked devices, we propose an energy saving strategy in the ``server-centric" data center network. Focusing on servers, we introduce a basic scheme based on the transition of automata. By changing efficiently from sleeping state to active state in different network traffic, servers save the energy. This scheme is self-adaptive and simple...
The core idea of cognitive radio technology is to realize the dynamic spectrum allocation and spectrum sharing through spectrum sensing and system learning. This paper sets the throughput and delays as the algorithm design target, puts forward a cognitive radio multi-channel routing algorithm based on a modified PCNN (MPCNN), which fully considered the multi-channel characteristic, through both the...
This paper addresses the NP-hard problem of switching off bundled links whilst retaining the QoS provided to existing applications. We propose a fast heuristic, called Multiple Paths by Shortest Path First (MSPF), and evaluated its performance against two state-of-the-art techniques: GreenTE, and FGH. MSPF improves the energy saving on average by 5% as compared to GreenTE with only 1% CPU time. While...
We reconsider guarded evaluation as a means to reduce FPGA dynamic power consumption. We augment and evaluate guarded evaluation as proposed in [1] after different stages of the FPGA CAD flow. Guarding later in the flow provides more feedback to the algorithm and yields a more effective cost-benefit analysis of newly added signals. Numerical results show that guarding later in the flow yields slightly...
To resolve channel interference and "Deafness" problem in cognitive wireless mesh network, a new Cross-layer Design based on Link Quality for Cognitive Wireless Mesh Networks is proposed. When the node chooses the channel, it is not only in accordance with the rank of channels, but also based on link quality. In this way, cross-layer technology can be effectively achieved, and network performance...
We propose a three-dimensional (3D) reconfigurable data-path accelerator which is capable of running partitioned large data flow graphs (DFGs) on the layers of 3D stack, while inter-layer connections are implemented by means of through-silicon vias (TSVs). A tool for mapping data flow graphs has been developed, and a key 3D-specific problem namely routing nets on 3D architecture has been discussed...
This paper introduces the design process of GARI, a novel routing protocol that incorporates cognitive networking concepts. This approach involves the monitoring of dynamic network conditions locally to adapt the routing strategy for a better performance of the global system. The result is a self-organizing network that meets the service requirements for the emerging applications of ad hoc networks.
The internet IP multicast technology has been extended to the field of wireless mobile. High performance routing algorithm is important for multimedia multicast in mobile wireless internet environment. This paper proposes a high performance multicast routing algorithm in mobile IP environment based on the super node set, which can reduce the cost of multicast generation tree, and greatly reduce the...
In this paper, we present a technology mapping and clustering tool for leakage power reduction in FPGAs with programmable, dual-VT logic blocks. The use of Reverse Back Bias (RBB) circuit techniques is recognized as one of the more promising strategies in mitigating leakage power, a critical problem in circuits deploying deep submicron process technologies. FPGAs with the ability to adjust fabric...
Flash data dissemination transmits time-critical data to distributed receivers in a timely manner, which is widely used in many mission-critical applications. However, existing flash data dissemination approaches fail to guarantee the timely transmission due to the unpredictability of the dissemination process. Overlay routing has been widely used as an efficient routing primitive for providing better...
A Hierarchical Torus Network (HTN) is a 2D-torus network of multiple basic modules, in which the basic modules are 3D-torus networks that are hierarchically interconnected for higher-level networks. Three deadlock-free adaptive routing algorithms called link-selection, channel-selection, and a combination of link-selection and channel-selection was proposed for the efficient use of physical links...
High-speed and low-power routers form the basic building blocks of on-die interconnect fabrics that are critical to overall throughput and energy efficiency of high performance systems [1,2]. Conventional routers use distinct logic blocks for routing data and handling arbitration [3,4]. At higher radices, connections between these blocks become a bottleneck, limiting router scalability and degrading...
A scalable architecture to design high radix switch fabric is presented. It uses circuit techniques to re-use existing input and output data buses and switching logic for fabric configuration and supporting multiple arbitration policies. In addition, it integrates a 4-level message-based priority arbitration for quality of service. Fine grain clock gating, tiled fabric topology and self-regenerating...
On chip many-core systems, evolving from prior multi-pro cessor systems, are considered as a promising solution to the performance scalability and power consumption problems. The long communication distance between the traditional multi-processors makes directory-based cache coherence protocols better solutions compared to bus-based snooping protocols even with the overheads from indirections. However,...
One of the major challenges in the process of three-dimensional integrated circuit fabrication is the manufacturing of through silicon vias (TSV). These TSVs compared with other connection elements require high manufacturing costs as well as large silicon area. In this paper, replication technique has been used to reduce the number of TSVs in 3D FPGAs. Replication is implemented for circuit input...
A reliable and variation-tolerant architecture for shared-L1 processor clusters is proposed. The architecture uses a single-cycle mesh of tree as the interconnection network between processors and a unified Tightly Coupled Data Memory (TCDM). The proposed technique is able to compensate the effect of process variation on processor to memory paths.
This paper presents a novel energy-efficient pulse switching protocol for ultra light-weight wireless network applications. The key idea is to abstract a single pulse, as opposed to multi-bit packets, as the information exchange mechanism. Pulse switching is shown to be sufficient for event sensing applications with binary sensing. Event sensing with conventional packet transport can be prohibitively...
In this paper, a new countermeasure against power and electromagnetic (EM) Side Channel Attacks (SCA) on FPGA implemented cryptographic algorithms is proposed. This structure mainly focuses on a critical vulnerability, Early Evaluation, also known as Early Propagation Effect (EPE), which exists in most conventional SCA-hardened DPL (Dual-rail with Precharge Logic) solutions. The main merit of this...
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