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In this paper a new gain stage for comparator-based switched-capacitor circuits (CBSC) is presented. In contrast with the conventional structure the proposed structure utilizes an extra comparator to make a variable comparator threshold, in order to attenuating the overshoot at the end of the coarse phase. To verify the idea, we designed a 2–1–1 cascaded MultiStage (MASH) ΔΣ modulator, based on the...
This paper presents an analog implementation of a digitally reprogrammable control for fixed frequency switching power converters. It is a recursive discrete time filter based on switched capacitor delay cells. The proposed circuit allows to synthesize different transfer functions in order to cope with the modifications in dynamics of power converters due to inputs or parameters variations. A prototype...
This work introduces a simple, background offset cancellation scheme for zero-crossing based circuits (ZCBC). The ZCBC architecture has been proposed as an alternative to op-amp based analog to digital converts (ADC) because it does not suffer from the gain, stability, and settling time trade off. However, offset remains as a challenge. This work demonstrates an input offset cancellation scheme that...
Q-band sub-harmonic mixers (SHMs) with and without delay compensation are demonstrated in this paper using 0.15-μm metamorphic high electron mobility transistor (mHEMT) technology. A conventional stacked-LO sub-harmonic mixing cell consists of two Gilbert cells in cascode with quadrature LO inputs. The proposed compensation core in parallel with the stacked-LO core improves the port-to-port isolation...
A method for realizing a phase shifter by employing switching transistors and transmission lines is proposed. The presented current switching phase shifter performs phase shifting by steering a current source to appropriate position on a transmission line. A 60-GHz phase shifter is implemented on a 65-nm CMOS technology using this method. The phase shifter can provide four quadrature phases for input...
Achieving faster dynamic response is one of the big challenges for the future microprocessor voltage regulators (VR). It is well known that the system bandwidth needs to be higher to get a faster dynamic response but the system bandwidth is usually limited by the phase shift near the switching frequency. In this paper, the existing theories for this phase shift and efforts to achieve a faster transient...
This paper describes the design of a dynamic state-space feedback gain scheduling controller for OBS burst scheduling. It can meet upper layer application requirements, while protecting the network from incurring severe burst loss and end-to-end delay. Through the use of gain scheduling to provide dynamic shifting between different models, the controller provides more accurate modelling than a single...
A low-power and high-speed ADC is crucial in a digital controller IC design. The Self-Strobe Delay-Line (SSDL) ADC architecture has been used because of its low-power and high-speed characteristics. However, the transconductance gain of the V-I converter in the SSDL ADC have not been optimized to have high sensitivity with low power consumption. In this paper, a differential sensing circuit was designed...
Inherent nonlinearity of pH processes causes that they are recognized as an appropriate test bench for evaluation of advanced controllers. Because of special characteristics of them, it is evident that adaptive controllers outperform others. This paper presents a comparison between a conventional adaptive controller and a switching multiple-model adaptive one in both regulation and disturbance rejection...
The effects of gate length Lg on the performance of a top gate silicon nanowire on insulator transistor are studied using three dimensional quantum simulation. From the study it is found that the inverse subthreshold slope and on/off current ratio are very sensitive to gate length. Significant improvement in subthreshold slope and on/off current ratio can be achieved using relatively longer gate with...
Inductor current tracking in high-frequency DC/DC converters is not effortless, especially when high output currents and low output voltages are demanded by the load. This paper proposes a guideline to design proper digital current-mode controlled (CMC) point-of-load (PoL) converts obtaining good accuracies in the inductor current tracking. The main idea is to obtain a equivalent voltage image of...
This paper considers fundamental limits on adaptive multiple-input multiple-output (MIMO) transmission with imperfect channel state information at the transmitter (CSIT). First, the achievable ergodic rates are derived for both single-user and multi-user MIMO systems with different CSIT assumptions, which shows that single-user MIMO is robust to imperfect CSIT while multiuser MIMO loses spatial multiplexing...
Directional antennas in sensor networks are receiving increasing interest and research due to the potential to increase throughput and reduce delay and interference, while requiring lower transmission power. Considering the stringent operation requirements (low duty-cycle) as MAC congestion problems in large multi-hop networks, WSN performance can benefit enormously from such directional capabilities...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
In this paper, we focus on investigating the L2 gain control synthesis problem of switched systems with input time-delay. Based on some basic and important lemmas, switched state feedback controllers guaranteeing that the corresponding closed-loop system is uniformly asymptotically stable with an L2 gain smaller than gamma is established. All the results in this paper are expressed in terms of linear...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
This paper describes how we can use existing mobile technology to track the vehicle. Here the embedded system along with the mobile is used to prevent the vehicle from being stolen and also if the vehicle is stolen then its location can be tracked. Mobile technology is the fastest growing communication mode. In todaypsilas mobile technology we all are acquainted with short message service (SMS). In...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
This paper presents a universal method for modeling the frequency response of comparators in switch- mode controllers. As the main non-linearity in most switch- mode controllers, understanding the comparator is the key to understanding the system. Based on discrete-time modeling, the proposed method is demonstrated to allow very precise predictions of comparator frequency response in a variety of...
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