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Networks-on-chip have a relative area and delay overhead compared to buses. These can be improved in application specific systems where heterogeneous communication infrastructures provide high bandwidth in a localized fashion and reduce underutilized resources. However, for general purpose architectures, design time techniques are not efficient. One approach for improving area and/or performance of...
In the routing architecture of a structured ASIC, crossbar is one of the most area efficient switch blocks. Nevertheless, dangling-wire occurs when there is a routing bend in crossbar switch. The dangling-wire incurs longer wire length as well as higher interconnection capacitance. In this paper, we are motivated to tackle dangling-wire routing issues for structured ASIC. We first propose a compact...
One of the important issues in power and performance trade off analysis in network on chip designs is communication. Communication portion in the power consumption of system on chip can be up to 50% of the whole power of consumption of the chip. This deems to be more important for network on chips which center around an intercommunication networks. Many networks on chip routers have been designed;...
In recent years, pre-fabricated design styles grow up rapidly to amortize the mask cost. However, the interconnection delay of the pre-fabricated design styles slows down the circuit performance due to the high capacitive load. In this paper, we propose a technique to insert dual-rail wires for pre-fabricated design styles. Furthermore, we propose an effective dual-rail insertion algorithm to reduce...
A customized reconfigurable interconnection network (CRIN) refers to a minimal switching network, yielding routing solutions for any element in a pre-given set of routing requirements. The CRIN design problem looks for the best performance and resource-flexibility trade-off between two extreme design contexts ASIC and FPGA. In this paper we give the modeling of this problem for both directed and undirected...
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