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In this work, we propose a novel basic element called delay chain feedback loop (DCFL) to generate metastability. Using 16 DCFLs with different delay chains, a new digital true random number generator (TRNG) is constructed. The new TRNG has been implemented on Altera Cyclone II and Altera Cyclone IV FPGAs. The experimental results show that the TRNG is true random which can pass both the NIST and...
SAKURA-G (Side-channel AttacK User Reference Architecture — G) board equipped with two Spartan-6 FPGAs was developed for physical attack experiments against a cryptographic circuit as a successor to SASEBO-GII. In this work we developed a clock manipulator for SAKURA-G, which generate glitch noises to provoke malfunctions on a cryptographic circuit. By using the DCM (Digital Clock Manager) and PLL...
FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systems-on-chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noise sources in electronic devices to generate confidential keys, initialization vectors, challenges, nonces, and random masks in cryptographic protocols. TRNGs aimed at cryptographic...
Radio Frequency Identification (RFID) has been widely used in many areas, but security issues still remain. To overcome these issues, RFID authentication protocols based on cryptographic algorithms have been developed. These protocols require implementing cryptographic components on the tag. In this paper, we focus on the lightweight stream ciphers and the lightweight hash functions that are vastly...
AES algorithm or Rijndael algorithm is a network security algorithm which is most commonly used in all types of wired and wireless digital communication networks for secure transmission of data between two end users, especially over a public network. This paper presents the hardware implementation of AES Rijndael Encryption and Decryption Algorithm by using Xilinx Virtex-7 FPGA. The hardware design...
An efficient compact implementation of the 128-bit SEED block cipher is presented in this paper. The proposed architecture achieves low level in hardware resources, so it is efficient for area constraints applications such as smart cards. The proposed implementation reaches a data throughput of 29.7 Mbps at 111 MHz clock frequency. The design was coded using VHDL language and for the hardware implementation,...
RSA (Rivest, Shamir, Adleman) is one of the most widely used cryptographic algorithms worldwide to perform data encryption and decryption. An essential step in RSA computation lies on its modular multiplication which is relatively expensive and time consuming to be implemented in hardware. This paper proposes two modular multiplication architectures based on modified serial montgomery algorithm for...
Secure System is significant part in the data communication. Randomization in the secret keys give raises to the security and complexity of the cryptography algorithms. However, the algorithms are compensating memory spaces and execution time. In Nov 2001 NIST select Advanced Encryption Standards (AES). Field programmable gate arrays (FPGAs), are reconfigurable in nature, low in price and. This paper...
Lightweight cryptography provides cryptographic algorithms for resource constrained devices and typically aims for low-cost ASIC applications like RFID tags. In addition, it also provides attractive performance — security trade-offs for FPGAs in scenarios with strict area constraints. This work presents FPGA implementations of the popular lightweight hash functions KECCAK-200 and KECCAK-400, PHOTON...
This paper investigates the state of the current high-level synthesis (HLS) tools by using Xilinx Vivado HLS for designing a cryptographic module based on Advanced Encryption Standard. The obtained results are compared with the results for the hand-written Register-Transfer Level (RTL) VHDL code to determine the suitability of the HLS-based approach for implementing cryptographic algorithms in hardware...
Using passwords for user authentication is still the most common method for many internet services and attacks on the password databases pose a severe threat. To reduce this risk, servers store password hashes, which were generated using special password-hashing functions, to slow down guessing attacks. The most frequently used functions of this type are PBKDF2, bcrypt and scrypt. In this paper, we...
A new cryptographic standard FPGA board SAKURA-G equipped with a 45-nm Xilinx Spartan-6 was developed to evaluate the security of cryptographic circuits against physical attacks and to measure the hardware performance of encryption algorithms. In addition to its rich array of capabilities, improved power analysis functionality over previous standard boards SASEBO-GII and SASEBO-G is demonstrated thorough...
Recent research has demonstrated that there is no sharp distinction between passive attacks based on side-channel leakage and active attacks based on fault injection. Fault behavior can be processed as side-channel information, offering all the benefits of Differential Power Analysis including noise averaging and hypothesis testing by correlation. This paper introduces Differential Fault Intensity...
Cryptographic hash functions have many security based applications, particularly in message authentication codes (MACs), digital signatures and data integrity. Secure Hash Algorithm-3 (SHA-3) is a new cryptographic hash algorithm that was selected on 2nd Oct '12 after a five year public contest organized by the National Institute of Standards and Technology (NIST), USA. This paper provides a unique...
A novel asynchronous S-Box design for AES cryptosystems is proposed and validated. The S-Box is considered as the most critical component in AES crypto-circuits since it consumes the most power and leaks the most information against side channel attacks. The proposed design completely based on a delay insensitive logic paradigm known as Null Conversion Logic (NCL). Asynchronous S-Box is based on self-time...
Elliptic curve cryptography is a rather new, efficient technology for security. However, its implementation is complex and software versions can be prohibitively slow. The main original contribution of this paper is the proposition of a highly parameterizable soft intellectual property core that implements all the operations needed to perform elliptic curve cryptography in hardware. This core supports...
Design of cryptographic applications need special care. For instance, physical attacks like Side-Channel Analysis (SCA) are able to recover the secret key, just by observing the activity of the computation, even for mathematically robust algorithms like AES. SCA considers the "leakage" of a well chosen intermediate variable correlated with the secret. Field programmable gate-arrays (FPGA)...
The SPACES project is a Japanese-French joint research project that aims to establish a new security evaluation methodology for cryptographic devices. We introduce one of the SPACES project outcomes associated with the development of the security evaluation platform for cryptographic devices. The new feature of the proposed system is to include a newly-developed Side-channel Attack Standard Evaluation...
We present a hardware-oriented architecture able to compute a 256-bit prime finite field multiplication efficiently. Taking advantage of the Karatsuba algorithm, the proposed architecture splits a 256-bit integer multiplication into fourteen 64-bit sub-products plus a number of additions that are performed using parallel and pipelined arrangements. The resulting 512-bit partial product is reduced...
Secure cryptographic hash functions are core components in many applications like challenge-response authentication systems or digital signature schemes. Many of these applications are used in cost-sensitive markets and thus slow budget implementations of such components are very important. In the present paper, we focus on the new SHA-3 competition, started by the National Institute of Standards...
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